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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t26-20020aa7d4da000000b004acb712d32csi17749294edr.233.2023.03.27.20.55.57; Mon, 27 Mar 2023 20:56:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=oIzcS2cR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232752AbjC1Dx3 (ORCPT + 99 others); Mon, 27 Mar 2023 23:53:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232764AbjC1DxH (ORCPT ); Mon, 27 Mar 2023 23:53:07 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C94372717 for ; Mon, 27 Mar 2023 20:52:58 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id d13so9680095pjh.0 for ; Mon, 27 Mar 2023 20:52:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679975578; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lJf8I19O2xeMdiC0tVrH0Ozu/0OD6wuIDQDeDtkRu8U=; b=oIzcS2cRoXTLIRBA/sASe19K/sDWSZlkZvX2MFKT4VHIs2okL1b2EhlAOc5tfcauGz yJmfFXk9TYVCWqXj4B8P722Mn/phLtT2jtlZrawwrIf3HGKOOXl30nqGGPN5NSykyuOh XB88YriT3z8R6PKlVOXi8Kms774Yh/sb+0UjZRaNoH56ldgyROacUxtpZPoZRoOZcCht 9EQCXr9VTzxJiBqL6w2Z8os1ZXUqEVPej1y6TcsScbGYCC8VEkDfEFs3/UYw9NKaFOLv h9XL5nxXd3Eu/3esufSkp0UKE8shfOeqq7SgHswm4o+pr0VLjta94qGnszEqb50m+KzV vwLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679975578; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lJf8I19O2xeMdiC0tVrH0Ozu/0OD6wuIDQDeDtkRu8U=; b=t7YPF0gQwxAnTDZD6Rf+750ovtxiBUTPzMaX0mB71IOTqBtjkFlVMoZB9WYWWXPVwh zWFcDLEuzir+ByMrJzFDhGhXIMlfsNvyOCO9EXn8f9d702xC8AePuiq/k1vu9OcLj9ba tquK4W2i3HyrvjKjcn1Ih6akT2sqK7qYk1cCW9Oi645jLplIlestshEQT6KbTqtmDBcf YmTTT+tZPbjWMevAcPJr/2+j5sleaRDejihfEcW5vgA34PfCvN36CfeACi8lRFXAn/Z8 XOT0agaw+BT3kE2YUlLPn/T6XWN+/+Ajcz5Vipr/wCJUl7F0PNtScmg8krO8+9n9wdEx nL2g== X-Gm-Message-State: AAQBX9ctmD7zHhCL0nE22G/fBGZhfEZeXnjYuaPvqhuT29T4WtRPBX3o 7TdxELx06l8usOglCpx5EHYGfg== X-Received: by 2002:a17:902:cec1:b0:1a1:a4eb:54de with SMTP id d1-20020a170902cec100b001a1a4eb54demr18515787plg.26.1679975577684; Mon, 27 Mar 2023 20:52:57 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.82.104]) by smtp.gmail.com with ESMTPSA id g6-20020a170902740600b0019cb534a824sm19880278pll.172.2023.03.27.20.52.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 20:52:57 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Palmer Dabbelt Subject: [PATCH v18 4/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs Date: Tue, 28 Mar 2023 09:22:20 +0530 Message-Id: <20230328035223.1480939-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230328035223.1480939-1-apatel@ventanamicro.com> References: <20230328035223.1480939-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the supervisor mode (i.e. RISC-V kernel) instead of using SBI calls. The upcoming AIA IMSIC devices allow direct IPI injection from the supervisor mode (i.e. RISC-V kernel). To support this, we extend the riscv_ipi_set_virq_range() function so that IPI provider (i.e. irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Acked-by: Palmer Dabbelt --- arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/sbi-ipi.c | 2 +- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 4fe7a8854c2e..c4b77017ec58 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr); +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) /* Check other CPUs stop or not */ bool smp_crash_stop_failed(void); @@ -96,10 +104,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c index 41981ab88493..a4559695ce62 100644 --- a/arch/riscv/kernel/sbi-ipi.c +++ b/arch/riscv/kernel/sbi-ipi.c @@ -72,6 +72,6 @@ void __init sbi_ipi_init(void) "irqchip/sbi-ipi:starting", sbi_ipi_starting_cpu, NULL); - riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, false); pr_info("providing IPIs using SBI IPI extension\n"); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 47e7ecfedb4d..5f985a197eff 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -177,7 +177,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; @@ -200,6 +203,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } static const char * const ipi_names[] = { diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 7ccc16dd6a76..9a55e733ae99 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -251,7 +251,7 @@ static int __init clint_timer_init_dt(struct device_node *np) } irq_set_chained_handler(clint_ipi_irq, clint_ipi_interrupt); - riscv_ipi_set_virq_range(rc, BITS_PER_BYTE); + riscv_ipi_set_virq_range(rc, BITS_PER_BYTE, true); clint_clear_ipi(); #endif -- 2.34.1