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 <87wn356ni4.fsf@oltmanns.dev> <20230327202045.ceeqqwjug4ktxtsf@penduick>
From:   Frank Oltmanns <frank@oltmanns.dev>
To:     Maxime Ripard <maxime@cerno.tech>
Cc:     Roman Beranek <romanberanek@icloud.com>,
        Chen-Yu Tsai <wens@csie.org>, David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        Samuel Holland <samuel@sholland.org>,
        dri-devel@lists.freedesktop.org,
        linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] drm/sun4i: uncouple DSI dotclock divider from
 TCON0_DCLK_REG
Date:   Tue, 28 Mar 2023 21:28:19 +0200
In-reply-to: <20230327202045.ceeqqwjug4ktxtsf@penduick>
Message-ID: <87bkkc3bzc.fsf@oltmanns.dev>
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Hi,

On 2023-03-27 at 22:20:45 +0200, Maxime Ripard <maxime@cerno.tech> wrote:
> Hi,
>
> On Sat, Mar 25, 2023 at 12:40:04PM +0100, Frank Oltmanns wrote:
[...]
>> Actually, I had the following third patch prepared that adjusted the dot=
clock rate so that the
>> required PLL rate is set. But again, this seems very indirect, so that=
=E2=80=99s why I refrained from
>> submitting it and I submitted the linked patch above instead.
>>
>> Anyway, here is the third proposal:
>>
>> =E2=80=94 a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
>> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
>> @@ -819,6 +819,34 @@ static void sun6i_dsi_encoder_disable(struct drm_en=
coder *encoder)
>>  	regulator_disable(dsi->regulator);
>>  }
>>
>> +static bool sun6i_dsi_encoder_mode_fixup(
>> =E2=81=83 struct drm_encoder *encoder,
>> =E2=81=83 const struct drm_display_mode *mode,
>> =E2=81=83 struct drm_display_mode *adjusted_mode)
>> +{
>> =E2=81=83 if (encoder->encoder_type =3D=3D DRM_MODE_ENCODER_DSI) {
>> =E2=81=83 /*
>> =E2=81=83 * For DSI the PLL rate has to respect the bits per pixel and
>> =E2=81=83 * number of lanes.
>> =E2=81=83 *
>> =E2=81=83 * According to the BSP code:
>> =E2=81=83 * PLL rate =3D DOTCLOCK * bpp / lanes
>> =E2=81=83 *
>> =E2=81=83 * Therefore, the clock has to be adjusted in order to set the
>> =E2=81=83 * correct PLL rate when actually setting the clock.
>> =E2=81=83 */
>> =E2=81=83 struct sun6i_dsi *dsi =3D encoder_to_sun6i_dsi(encoder);
>> =E2=81=83 struct mipi_dsi_device *device =3D dsi->device;
>> =E2=81=83 u8 bpp =3D mipi_dsi_pixel_format_to_bpp(device->format);
>> =E2=81=83 u8 lanes =3D device->lanes;
>> =E2=81=83
>>
>> =E2=81=83 adjusted_mode->crtc_clock =3D mode->crtc_clock
>> =E2=81=83 * bpp / (lanes * SUN6I_DSI_TCON_DIV);
>> =E2=81=83 }
>> =E2=81=83
>>
>> =E2=81=83 return true;
>> +}
>> =E2=81=83 static int sun6i_dsi_get_modes(struct drm_connector *connector)
>>   {
>>       struct sun6i_dsi *dsi =3D connector_to_sun6i_dsi(connector);
>> @@ -851,6 +879,7 @@ static const struct drm_connector_funcs sun6i_dsi_co=
nnector_funcs =3D {
>>  static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs=
 =3D {
>>  	.disable	=3D sun6i_dsi_encoder_disable,
>>  	.enable		=3D sun6i_dsi_encoder_enable,
>> =E2=81=83 .mode_fixup =3D sun6i_dsi_encoder_mode_fixup,
>>   };
>
> It's not clear to me what this patch is supposed to be doing, there's no =
mode_fixup implementation
> upstream?
>

Sorry, my mail client tried some fancy formatting. :(

This is the patch again.

--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -819,6 +819,34 @@ static void sun6i_dsi_encoder_disable(struct drm_encod=
er *encoder)
 	regulator_disable(dsi->regulator);
 }

+static bool sun6i_dsi_encoder_mode_fixup(
+				   struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	if (encoder->encoder_type =3D=3D DRM_MODE_ENCODER_DSI) {
+		/*
+		 * For DSI the PLL rate has to respect the bits per pixel and
+		 * number of lanes.
+		 *
+		 * According to the BSP code:
+		 * PLL rate =3D DOTCLOCK * bpp / lanes
+		 *
+		 * Therefore, the clock has to be adjusted in order to set the
+		 * correct PLL rate when actually setting the clock.
+		 */
+		struct sun6i_dsi *dsi =3D encoder_to_sun6i_dsi(encoder);
+		struct mipi_dsi_device *device =3D dsi->device;
+		u8 bpp =3D mipi_dsi_pixel_format_to_bpp(device->format);
+		u8 lanes =3D device->lanes;
+
+		adjusted_mode->crtc_clock =3D mode->crtc_clock
+				 * bpp / (lanes * SUN6I_DSI_TCON_DIV);
+	}
+
+	return true;
+}
+
 static int sun6i_dsi_get_modes(struct drm_connector *connector)
 {
 	struct sun6i_dsi *dsi =3D connector_to_sun6i_dsi(connector);
@@ -851,6 +879,7 @@ static const struct drm_connector_funcs sun6i_dsi_conne=
ctor_funcs =3D {
 static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs =
=3D {
 	.disable	=3D sun6i_dsi_encoder_disable,
 	.enable		=3D sun6i_dsi_encoder_enable,
+	.mode_fixup	=3D sun6i_dsi_encoder_mode_fixup,
 };

 static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,


I still like the original patch better, but I'd be happy to submit this
as a proper patch, if this is more to your liking.

Thanks,
  Frank


> Maxime
>
--