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Date:   Wed, 29 Mar 2023 07:50:52 -0500
From:   Nishanth Menon <nm@ti.com>
To:     Hari Nagalla <hnagalla@ti.com>
CC:     <vigneshr@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/3] arm64: dts: ti: k3-j784s4-main: Add C71x DSP nodes
Message-ID: <20230329125052.7uoivy2hpkhae4i3@blimp>
References: <20230329093627.30719-1-hnagalla@ti.com>
 <20230329093627.30719-4-hnagalla@ti.com>
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On 04:36-20230329, Hari Nagalla wrote:
> The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage
> domain. The functionality of these DSP subsystems is similar to the C71x
> DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of
> L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem
> has a CMMU but is not currently used. The inter-processor communication
> between the main A72 cores and the C71x DSPs is achieved through shared
> memory and mailboxes. Add the DT nodes for these DSP processor sub-systems.
> 
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 52 ++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 53d337ea35fb..9af0bab5382a 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1152,4 +1152,56 @@
>  
>  		};
>  	};
> +
> +	c71_0: dsp@64800000 {
> +		compatible = "ti,j721s2-c71-dsp";
> +		reg = <0x00 0x64800000 0x00 0x00080000>,
> +		      <0x00 0x64e00000 0x00 0x0000c000>;
> +		reg-names = "l2sram", "l1dram";
> +		ti,sci = <&sms>;
> +		ti,sci-dev-id = <30>;
> +		ti,sci-proc-ids = <0x30 0xff>;
> +		resets = <&k3_reset 30 1>;
> +		firmware-name = "j784s4-c71_0-fw";
> +		status = "disabled";

And why are these disabled by default?

> +	};
> +
> +	c71_1: dsp@65800000 {
> +		compatible = "ti,j721s2-c71-dsp";
> +		reg = <0x00 0x65800000 0x00 0x00080000>,
> +		      <0x00 0x65e00000 0x00 0x0000c000>;
> +		reg-names = "l2sram", "l1dram";
> +		ti,sci = <&sms>;
> +		ti,sci-dev-id = <33>;
> +		ti,sci-proc-ids = <0x31 0xff>;
> +		resets = <&k3_reset 33 1>;
> +		firmware-name = "j784s4-c71_1-fw";
> +		status = "disabled";
> +	};
> +
> +	c71_2: dsp@66800000 {
> +		compatible = "ti,j721s2-c71-dsp";
> +		reg = <0x00 0x66800000 0x00 0x00080000>,
> +		      <0x00 0x66e00000 0x00 0x0000c000>;
> +		reg-names = "l2sram", "l1dram";
> +		ti,sci = <&sms>;
> +		ti,sci-dev-id = <37>;
> +		ti,sci-proc-ids = <0x32 0xff>;
> +		resets = <&k3_reset 37 1>;
> +		firmware-name = "j784s4-c71_2-fw";
> +		status = "disabled";
> +	};
> +
> +	c71_3: dsp@67800000 {
> +		compatible = "ti,j721s2-c71-dsp";
> +		reg = <0x00 0x67800000 0x00 0x00080000>,
> +		      <0x00 0x67e00000 0x00 0x0000c000>;
> +		reg-names = "l2sram", "l1dram";
> +		ti,sci = <&sms>;
> +		ti,sci-dev-id = <40>;
> +		ti,sci-proc-ids = <0x33 0xff>;
> +		resets = <&k3_reset 40 1>;
> +		firmware-name = "j784s4-c71_3-fw";
> +		status = "disabled";
> +	};
>  };
> -- 
> 2.17.1
> 

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D