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Date:   Wed, 29 Mar 2023 08:23:08 -0500
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Subject: Re: [PATCH 1/2] drm/amdgpu: Reset GPU on S0ix when device supports
 BOCO
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To:     Kai-Heng Feng <kai.heng.feng@canonical.com>,
        alexander.deucher@amd.com, christian.koenig@amd.com,
        Xinhui.Pan@amd.com
Cc:     David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
        Bokun Zhang <Bokun.Zhang@amd.com>,
        Maxime Ripard <maxime@cerno.tech>,
        Tim Huang <tim.huang@amd.com>,
        Jingyu Wang <jingyuwang_vip@163.com>,
        "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
        Hans de Goede <hdegoede@redhat.com>,
        Hawking Zhang <Hawking.Zhang@amd.com>,
        Lijo Lazar <lijo.lazar@amd.com>,
        Andrey Grodzovsky <andrey.grodzovsky@amd.com>,
        YiPeng Chai <YiPeng.Chai@amd.com>,
        Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>,
        Evan Quan <evan.quan@amd.com>,
        Guchun Chen <guchun.chen@amd.com>,
        =?UTF-8?Q?Michel_D=c3=a4nzer?= <mdaenzer@redhat.com>,
        Kenneth Feng <kenneth.feng@amd.com>,
        Jiansong Chen <Jiansong.Chen@amd.com>,
        amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
References: <20230329095933.1203559-1-kai.heng.feng@canonical.com>
From:   Mario Limonciello <mario.limonciello@amd.com>
In-Reply-To: <20230329095933.1203559-1-kai.heng.feng@canonical.com>
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 =?utf-8?B?cldWV1NYbFhpT0NKc3V0Q25SUVVEdVN1MlBVZEg5b1hqa0FEUkRxYURERGcv?=
 =?utf-8?B?VmMyeG5ZMURLeUVpd3pIS1A0NDVEL1RtaytvZUxFZEdvbmlETDllM0x0Nzls?=
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 =?utf-8?B?aDJTNW1kN2FEL1I2RFB5alE2SWMwc2tjdE1uQlVJcG9ka2l5ajN3V1hDUDRx?=
 =?utf-8?B?eTJ6U3JrT3RoN3liZVJNbnorMGVvLzhBVExuZjVYc1VWNnRQaGowSnJ1TEN2?=
 =?utf-8?B?ZlpHWnNhdXZFbThGcE9rVXlud2dQeGN3alJnS3JXbmJjTTJQcCt1dnJFeUZB?=
 =?utf-8?B?eEFwZERTSWkxeVZRUkFzamFyY1I5OWNEQ1RCOFFrcVQzWkhJbGlkaUdVRE44?=
 =?utf-8?B?Rk91ZFlwT29GNFhYNWQzdDZobFcvaEl5VE1vV1F1bGhxVEhJWUdqSHN0eWpU?=
 =?utf-8?B?MDV5bk9lRWxEamtHblgzUE5FNDJpRnhrR1Vrd0N2RFVXVzV1VGhVaUlsdmJa?=
 =?utf-8?B?VnlEZzZxdVJlcVgycnZtbmdhSnI0NlJaZzJGNkJrYU5NNnorcFBJVXZNQnZO?=
 =?utf-8?B?bW5rN2Zva05mWXFDUjNOdUZKR3hDNXdKTHcraW5WMkxRNnk0Qk1EVlJsSXZT?=
 =?utf-8?B?M3k1VUQ0ME1IMVlodlZTdEtZc2phNXUrcitVeitaUU9tWjMrdXIrc2xveHo1?=
 =?utf-8?B?Rld4WWNZUFN0MW5NME1aeHlBQ1pkYjc2Y0lDSUtQVWsvUzBPcXdNeWJFSU9P?=
 =?utf-8?B?Qys5RWZtM3ZpYkpTb1RGMUdjd2MxNWZ5Tkd1MnNJVlBjeUptNkRVa29LRzVH?=
 =?utf-8?B?MFd0dklwRlZhdXVlS25haUNGK2Z3S1d1Q1lyZkxmSGM3a2U0YVJ2Vko0UW9x?=
 =?utf-8?B?OFQ1cHpwWjQ4STlqUWpoM0dDMnZkMU82MytiVHRyM29YQldub2RuM1FoWU5r?=
 =?utf-8?B?Q1ZNcFIyQ1VHREtaSGpKNTk4a3d6VFRIdEJzVHFYRDMyakpaS1gyRUpuMUJN?=
 =?utf-8?B?S0ozWUFpQXZMRmxDWkZrbXF6eEFMQUtoZWhTSFhmSm9haGkzeGhQLzVhb0Vq?=
 =?utf-8?B?blFnWjBYUEFISm1YazdzSlhGT1ZxRU41VzM1V21nMll6Nzh0S3I5UmFRaGwx?=
 =?utf-8?B?MTJNbWZIMU40SjBML3I3OVZMbnh4YzFWSTVzUThpa0wwV0czd1NFQVRVTWhT?=
 =?utf-8?B?azAzUUVNLzZKbVlFRmNlT0QzbVFzb0ZXZFA3TFo5TFcydzNyN1JGQkpwV3pG?=
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 =?utf-8?B?T05OVlVVb0VCUHcyVXFHd0pSaEFBb1o1eDN5MFVMUWlXNmJWREQ0VVl1Sis2?=
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On 3/29/23 04:59, Kai-Heng Feng wrote:
> When the power is lost due to ACPI power resources being turned off, the
> driver should reset the GPU so it can work anew.
>
> First, _PR3 support of the hierarchy needs to be found correctly. Since
> the GPU on some discrete GFX cards is behind a PCIe switch, checking the
> _PR3 on downstream port alone is not enough, as the _PR3 can associate
> to the root port above the PCIe switch.

I think this should be split into two commits:

* One of them to look at _PR3 further up in hierarchy to fix indication
for BOCO support.

* One to adjust policy for whether to reset


> Once the _PR3 is found and BOCO support is correctly marked, use that
> information to inform the GPU should be reset. This solves an issue that
> system freeze on a Intel ADL desktop that uses S0ix for sleep and D3cold
> is supported for the GFX slot.

I'm worried this is still papering over an underlying issue with L0s
handling on ALD + Navi1x/Navi2x.

Also, what about runtime suspend?  If you unplug the monitor from this
dGPU and interact with it over SSH it should go into runtime suspend.

Is it working properly for that case now?

>
> Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default")
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1885
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2458
> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c   |  3 +++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  7 ++++++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 12 +++++-------
>   3 files changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index 60b1857f469e..407456ac0e84 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -987,6 +987,9 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev)
>   	if (amdgpu_sriov_vf(adev))
>   		return false;
>   
> +	if (amdgpu_device_supports_boco(adev_to_drm(adev)))
> +		return true;
> +
>   #if IS_ENABLED(CONFIG_SUSPEND)
>   	return pm_suspend_target_state != PM_SUSPEND_TO_IDLE;
>   #else
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index f5658359ff5c..d56b7a2bafa6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2181,7 +2181,12 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
>   
>   	if (!(adev->flags & AMD_IS_APU)) {
>   		parent = pci_upstream_bridge(adev->pdev);
> -		adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
> +		do {
> +			if (pci_pr3_present(parent)) {
> +				adev->has_pr3 = true;
> +				break;
> +			}
> +		} while ((parent = pci_upstream_bridge(parent)));
>   	}
>   
>   	amdgpu_amdkfd_device_probe(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index ba5def374368..5d81fcac4b0a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2415,10 +2415,11 @@ static int amdgpu_pmops_suspend(struct device *dev)
>   	struct drm_device *drm_dev = dev_get_drvdata(dev);
>   	struct amdgpu_device *adev = drm_to_adev(drm_dev);
>   
> -	if (amdgpu_acpi_is_s0ix_active(adev))
> -		adev->in_s0ix = true;
> -	else if (amdgpu_acpi_is_s3_active(adev))
> +	if (amdgpu_acpi_is_s3_active(adev) ||
> +	    amdgpu_device_supports_boco(drm_dev))
>   		adev->in_s3 = true;
> +	else if (amdgpu_acpi_is_s0ix_active(adev))
> +		adev->in_s0ix = true;
>   	if (!adev->in_s0ix && !adev->in_s3)
>   		return 0;
>   	return amdgpu_device_suspend(drm_dev, true);
> @@ -2449,10 +2450,7 @@ static int amdgpu_pmops_resume(struct device *dev)
>   		adev->no_hw_access = true;
>   
>   	r = amdgpu_device_resume(drm_dev, true);
> -	if (amdgpu_acpi_is_s0ix_active(adev))
> -		adev->in_s0ix = false;
> -	else
> -		adev->in_s3 = false;
> +	adev->in_s0ix = adev->in_s3 = false;
>   	return r;
>   }
>