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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s5-20020a63e805000000b00502effd3bb9si32031896pgh.521.2023.03.29.06.26.47; Wed, 29 Mar 2023 06:27:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="Wq/ZHR3g"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230303AbjC2NZJ (ORCPT + 99 others); Wed, 29 Mar 2023 09:25:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230044AbjC2NZH (ORCPT ); Wed, 29 Mar 2023 09:25:07 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0220646BF; Wed, 29 Mar 2023 06:24:33 -0700 (PDT) Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 85F5D6603173; Wed, 29 Mar 2023 14:24:30 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680096271; bh=QC+TVvnacafeIHmbzTyunv64Km/TSjEM1hbjaqYCL0E=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Wq/ZHR3gmA5TcS6nh98MqlxCjA+ciMEgTZAOYfId/MOzbR42VJJGeD9AzSnoAC7hK HKU+plaSGCBXOTMucZfWhLBmsmqcbCnsS6TOV6AeZBJazvS0ENHSO9whtJDnRIPiyn w3bP8f9jcIFpn3ZRO3q3swCiuXkviDRw4+nntIS8HiuOe2puLgiVOf5qiqkXVgj/OR SBh9fig+Qw9uJUh4iyTG+o5NXU43neKkZn9Qa8FRUcpZ4dZRmAkxz3Ut/haLXwwaE3 0HORYdmXIHgOMHljij5NqxbpB0UJkmdTxWCxT/X9Q8HbZ9NUYT0AzAe/KK9iUbdcj8 HovQFH0OkXDcA== Message-ID: <67af041d-cce5-8c3b-e979-7b95a6a7a149@collabora.com> Date: Wed, 29 Mar 2023 15:24:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v3 09/17] arm64: dts: mediatek: add mmc support for mt8365-evk Content-Language: en-US To: Alexandre Mergnat , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chaotian Jing , Ulf Hansson , Wenbin Mei , Linus Walleij , Zhiyong Tao , =?UTF-8?Q?Bernhard_Rosenkr=c3=a4nzer?= Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, Alexandre Bailon , Fabien Parent , Amjad Ouled-Ameur References: <20230203-evk-board-support-v3-0-0003e80e0095@baylibre.com> <20230203-evk-board-support-v3-9-0003e80e0095@baylibre.com> From: AngeloGioacchino Del Regno In-Reply-To: <20230203-evk-board-support-v3-9-0003e80e0095@baylibre.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Il 29/03/23 10:54, Alexandre Mergnat ha scritto: > - Add EMMC support on mmc0 (internal memory) > - Add SD-UHS support on mmc1 (external memory) > > Signed-off-by: Alexandre Mergnat > --- > arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 138 ++++++++++++++++++++++++++++ > 1 file changed, 138 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > index 2f88562c638a..b5d018686cbe 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > @@ -97,6 +97,42 @@ &i2c0 { > #size-cells = <0>; > }; > > +&mmc0 { > + pinctrl-names = "default", "state_uhs"; > + pinctrl-0 = <&mmc0_default_pins>; > + pinctrl-1 = <&mmc0_uhs_pins>; > + bus-width = <8>; > + max-frequency = <200000000>; > + cap-mmc-highspeed; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + cap-mmc-hw-reset; > + no-sdio; > + no-sd; > + hs400-ds-delay = <0x12012>; > + vmmc-supply = <&mt6357_vemc_reg>; > + vqmmc-supply = <&mt6357_vio18_reg>; > + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; > + non-removable; That's a bit messy :-) Can we please reorder this by name? assigned-clocks.... bus-width cap.... hs400-ds-delay max... mmc-hs... no... non-rem... pinctrl... vxxxx-supply status .... ...Actually the same comment also applies to mmc1. Cheers, Angelo