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Wed, 29 Mar 2023 10:12:44 -0700 Received: from [10.41.21.79] (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 29 Mar 2023 10:12:38 -0700 Message-ID: <0b393600-3f08-c2e8-9b02-664c6a984de1@nvidia.com> Date: Wed, 29 Mar 2023 22:42:36 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [Patch v4 01/10] dt-bindings: memory: tegra: add bpmp ref in tegra234-mc node To: Thierry Reding , Krzysztof Kozlowski CC: , , , , , , , , , , , , , , , , , , , , Sumit Gupta References: <20230327161426.32639-1-sumitg@nvidia.com> <20230327161426.32639-2-sumitg@nvidia.com> <787f656a-223d-5eed-e311-9cc7a6c46452@linaro.org> <79d8044f-ce68-463e-66f7-8755e253bc99@linaro.org> Content-Language: en-US From: Sumit Gupta In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT103:EE_|DM4PR12MB7501:EE_ X-MS-Office365-Filtering-Correlation-Id: b1c1edd0-0025-4b75-dc52-08db3078d6bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2023 17:12:55.6686 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1c1edd0-0025-4b75-dc52-08db3078d6bc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7501 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,NICE_REPLY_A, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28/03/23 18:18, Thierry Reding wrote: > On Tue, Mar 28, 2023 at 01:22:26PM +0200, Krzysztof Kozlowski wrote: >> On 28/03/2023 12:48, Thierry Reding wrote: >>> On Tue, Mar 28, 2023 at 09:23:04AM +0200, Krzysztof Kozlowski wrote: >>>> On 27/03/2023 18:14, Sumit Gupta wrote: >>>>> For Tegra234, add the "nvidia,bpmp" property within the Memory >>>>> Controller (MC) node to reference BPMP node. This is needed in >>>>> the MC driver to pass the client info to the BPMP-FW when memory >>>>> interconnect support is available. >>>>> >>>>> Signed-off-by: Sumit Gupta >>>>> --- >>>>> .../bindings/memory-controllers/nvidia,tegra186-mc.yaml | 7 +++++++ >>>>> 1 file changed, 7 insertions(+) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >>>>> index 935d63d181d9..398d27bb2373 100644 >>>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >>>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >>>>> @@ -58,6 +58,10 @@ properties: >>>>> "#interconnect-cells": >>>>> const: 1 >>>>> >>>>> + nvidia,bpmp: >>>>> + $ref: /schemas/types.yaml#/definitions/phandle >>>>> + description: phandle of the node representing the BPMP >>>> >>>> Why do you need this multiple times? Both in parent and all external-mc >>>> children? >>> >>> We've had nvidia,bpmp in the external memory controller node since >>> basically the beginning because we've always needed it there. For newer >>> chips we now also need it for the memory controller. >>> >>> Ideally I think we would only have this in the MC and have the EMC >>> driver reference it via the EMC's parent (i.e. MC), but that would break >>> backwards-compatibility. Reaching into the EMC's DT node from the MC was >>> another option that we discussed internally, but it didn't look right >>> given how this is also needed by the MC. >>> >>> One thing we could potentially do is deprecate the nvidia,bpmp phandle >>> in the EMC and only keep it as a fallback in the drivers in case the >>> parent MC doesn't find it's own in the DT. >> >> Yes, deprecation would answer to my question. > > Okay, great. Sumit, you can resolve this by adding a "deprecated: true" > to the EMC's nvidia,bpmp property schema. In the driver we can then try > to look at the MC's ->bpmp and if it exists reuse that. If it doesn't > exist, we can keep the existing lookup as a fallback for device trees > that haven't been updated yet. We can't use MC's->bpmp in the EMC driver's probe as it will be NULL. This is because MC driver uses "arch_initcall" and gets probed earlier than BPMP. We can do this in another way as below change. This way we can use the existing "nvidia,bpmp" property from EMC node and don't need to move it to the MC node. Please share if this change sounds OK. +++ b/drivers/memory/tegra/tegra186-emc.c @@ static int tegra186_emc_probe(struct platform_device *pdev) - if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { mc->bwmgr_mrq_supported = true; + mc->bpmp = emc->bpmp; + } } return 0; put_bpmp: - tegra_bpmp_put(emc->bpmp); + if (IS_ERR_OR_NULL(mc->bpmp)) + tegra_bpmp_put(emc->bpmp); return err; } static int tegra186_emc_remove(struct platform_device *pdev) { struct tegra186_emc *emc = platform_get_drvdata(pdev); + struct tegra_mc *mc = dev_get_drvdata(emc->dev->parent); debugfs_remove_recursive(emc->debugfs.root); - tegra_bpmp_put(emc->bpmp); + if (IS_ERR_OR_NULL(mc->bpmp)) + tegra_bpmp_put(emc->bpmp); return 0; }