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Date:   Thu, 30 Mar 2023 13:30:16 +0530
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Subject: Re: [Patch v4 10/10] PCI: tegra194: add interconnect support in
 Tegra234
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To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     <treding@nvidia.com>, <krzysztof.kozlowski@linaro.org>,
        <dmitry.osipenko@collabora.com>, <viresh.kumar@linaro.org>,
        <rafael@kernel.org>, <jonathanh@nvidia.com>, <robh+dt@kernel.org>,
        <lpieralisi@kernel.org>, <linux-kernel@vger.kernel.org>,
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        <mmaddireddy@nvidia.com>, <kw@linux.com>, <bhelgaas@google.com>,
        <vidyas@nvidia.com>, <sanjayc@nvidia.com>, <ksitaraman@nvidia.com>,
        <ishah@nvidia.com>, <bbasu@nvidia.com>,
        Sumit Gupta <sumitg@nvidia.com>
References: <20230329191703.GA3076491@bhelgaas>
From:   Sumit Gupta <sumitg@nvidia.com>
In-Reply-To: <20230329191703.GA3076491@bhelgaas>
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On 30/03/23 00:47, Bjorn Helgaas wrote:
> External email: Use caution opening links or attachments
> 
> 
> On Wed, Mar 29, 2023 at 11:28:40PM +0530, Sumit Gupta wrote:
>> On 29/03/23 22:29, Bjorn Helgaas wrote:
>>> On Wed, Mar 29, 2023 at 02:44:34PM +0530, Sumit Gupta wrote:
>>>> On 28/03/23 23:23, Bjorn Helgaas wrote:
>>>>>> +static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie)
>>>>>> +{
>>>>>> +     struct dw_pcie *pci = &pcie->pci;
>>>>>> +     u32 val, speed, width;
>>>>>> +
>>>>>> +     val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
>>>>>> +
>>>>>> +     speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
>>>>>> +     width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);
>>>>>> +
>>>>>> +     val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) / BITS_PER_BYTE);
>>>>>> +
>>>>>> +     if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0))
>>>>>> +             dev_err(pcie->dev, "can't set bw[%u]\n", val);
>>>>>> +
>>>>>> +     clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
>>>>>
>>>>> Array bounds violation; PCI_EXP_LNKSTA_CLS is 0x000f, so possible
>>>>> speed (CLS) values are 0..0xf and "speed - 1" values are -1..0xe.
>>>>>
>>>>> pcie_gen_freq[] is of size 4 (valid indices 0..3).
>>>>>
>>>>> I see that you're just *moving* this code, but might as well fix it.
>>>>>
>>>> Thank you for the review.
>>>> Will include the below change in the same patch. Please let me know if any
>>>> issue.
>>>>
>>>>    -       clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
>>>>    +       if (speed && (speed <= ARRAY_SIZE(pcie_gen_freq)))
>>>>    +               clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
>>>>    +       else
>>>>    +               clk_set_rate(pcie->core_clk, pcie_gen_freq[0]);
>>>
>>> I didn't notice that speed is a u32, so -1 is not a possible value.
>>> Also, it's used earlier for PCIE_SPEED2MBS_ENC(), so you could do
>>> something like this:
>>>
>>>     speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val) - 1;
>>>     if (speed >= ARRAY_SIZE(pcie_gen_freq))
>>>       speed = 0;
>>>
>>>     val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) /
>>>           BITS_PER_BYTE);
>>>     ...
>>>     clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
>>
>> I tried this change but PCIE_SPEED2MBS_ENC gives zero when speed value is
>> one. The speed value ranges from "1 to 4" and for value "1",
>> pcie_link_speed[speed] gives '0xff'.
> 
> Oh, my fault, sorry!  I thought both places indexed the same array,
> but the first is pcie_link_speed[] (where all the possible values
> (0..0xf) are valid indices) and the second is pcie_gen_freq[] (where
> only 0..3 are valid).
> 
>> The below change works fine. Please share if its OK to add it in patch.
>>
>>    speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
>>    if (!speed || speed >= ARRAY_SIZE(pcie_gen_freq))
>>            speed = 1;
>>
>>    val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) /
>> BITS_PER_BYTE);
> 
> So I don't think you need to clamp "speed" for indexing
> pcie_link_speed[] at all.
> 
>>    if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0))
>>            dev_err(pcie->dev, "can't set bw[%u]\n", val);
>>
>>    clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
> 
> What if you added a 0th entry to pcie_gen_freq[] so you can index it
> directly with the PCI_EXP_LNKSTA_CLS value the same way as
> pcie_link_speed[]?  Then you wouldn't need the "- 1" and only have to
> worry about going off the end:
> 
>    static const unsigned int pcie_gen_freq[] = {
>      GEN1_CORE_CLK_FREQ,   /* PCI_EXP_LNKSTA_CLS == 0; undefined */
>      GEN1_CORE_CLK_FREQ,
>      GEN2_CORE_CLK_FREQ,
>      GEN3_CORE_CLK_FREQ,
>      GEN4_CORE_CLK_FREQ,
>    };
> 
>    speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
> 
>    val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) /
>          BITS_PER_BYTE);
> 
>    if (speed >= ARRAY_SIZE(pcie_gen_freq))
>      speed = 0;
>    clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
> 
> Bjorn

Yes, this is working fine. Will add it in the patch.

Thank you,
Sumit Gupta