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From:   Mike Leach <mike.leach@linaro.org>
To:     linux-perf-users@vger.kernel.org,
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Cc:     suzuki.poulose@arm.com, leo.yan@linaro.org, peterz@infradead.org,
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        namhyung@kernel.org, gankulkarni@os.amperecomputing.com,
        darren@os.amperecomputing.com, Mike Leach <mike.leach@linaro.org>
Subject: [PATCH v9 0/3] perf: cs-etm: Update perf to handle new Coresight Trace ID
Date:   Fri, 31 Mar 2023 06:56:42 +0100
Message-Id: <20230331055645.26918-1-mike.leach@linaro.org>
Precedence: bulk

The original method for allocating trace source ID values to sources was
to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10).
The STM was allocated ID 0x1.

This mechanism is broken for systems with more than 47 cores.

The kernel related patches the provide a fixed Trace ID allocation mechanism
are now upstreamed.

This patchset updates the perf code to handle the changes to the trace ID
notification mechanism that now uses the PERF_RECORD_AUX_OUTPUT_HW_ID
packet to set Trace ID in the perf ETM decoders.

Applies and test oo perf/core

Changes since v8:
1. Fix build issues
2. Fix implicit function problem

Changes since v7:
Split from original patchset [1] to be sent separately as kernel related
patches are now upstream.

[1] https://lore.kernel.org/linux-arm-kernel/20230116124928.5440-1-mike.leach@linaro.org/

Mike Leach (3):
  perf: cs-etm: Move mapping of Trace ID and cpu into helper function
  perf: cs-etm: Update record event to use new Trace ID protocol
  perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet

 tools/include/linux/coresight-pmu.h           |  47 ++-
 tools/perf/arch/arm/util/cs-etm.c             |  27 +-
 tools/perf/util/cs-etm-base.c                 |   3 +-
 .../perf/util/cs-etm-decoder/cs-etm-decoder.c |   7 +
 tools/perf/util/cs-etm.c                      | 326 +++++++++++++++---
 tools/perf/util/cs-etm.h                      |  14 +-
 6 files changed, 356 insertions(+), 68 deletions(-)

-- 
2.17.1