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From:   Siddharth Vadapalli <s-vadapalli@ti.com>
To:     <vkoul@kernel.org>, <kishon@kernel.org>, <rogerq@kernel.org>
CC:     <linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <srk@ti.com>,
        <s-vadapalli@ti.com>
Subject: [PATCH 0/2] PHY-GMII-SEL: Add support for J784S4 SoC
Date:   Fri, 31 Mar 2023 11:55:19 +0530
Message-ID: <20230331062521.529005-1-s-vadapalli@ti.com>
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Hello,

This series TI's J784S4 SoC. A new compatible is added for the J784S4 SoC,
with QSGMII mode enabled. Also, the CPSW9G instance of J784S4 SoC supports
USXGMII mode. Thus, add support to configure USXGMII mode.

Note:
This series is based on top of the following series:
https://lore.kernel.org/r/20230309063514.398705-1-s-vadapalli@ti.com/

The patch corresponding to the device-tree bindings for the compatible
"ti,j784s4-cpsw9g-phy-gmii-sel" is posted at:
https://lore.kernel.org/r/20230315092408.1722114-1-s-vadapalli@ti.com
Since the above patch has received an Acked-by from Krzysztof Kozlowski,
I am posting this series using the compatible.

Regards,
Siddharth.

Siddharth Vadapalli (2):
  phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4
  phy: ti: gmii-sel: Enable USXGMII mode for J784S4

 drivers/phy/ti/phy-gmii-sel.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

-- 
2.25.1