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Date:   Fri, 31 Mar 2023 11:21:56 +0100
Message-ID: <868rfdw797.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Peng Fan <peng.fan@nxp.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: gic700 shareability question
In-Reply-To: <DU0PR04MB9417388F9BDD73080294FA8E88889@DU0PR04MB9417.eurprd04.prod.outlook.com>
References: <DU0PR04MB9417388F9BDD73080294FA8E88889@DU0PR04MB9417.eurprd04.prod.outlook.com>
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+ Lorenzo

On Tue, 28 Mar 2023 13:48:19 +0100,
Peng Fan <peng.fan@nxp.com> wrote:
> 
> Hi Marc,
> 
> We have an SoC that use GIC-700, but not support shareability,

Define this. The IP does support shareability, but your integration
doesn't?

> Currently I just hack the code as below. Do you think it is feasible
> to add firmware bindings such that these can be used to define 
> the correct shareability/cacheability instead of relying on the
> programmability of the CBASER register?
> 
> Saying with "broken-shareability", we just clear all the shareability
> settings.

This is the same thing as the Rockchip crap, so you are in good
company.

I've repeatedly stated that this needs to be handled:

- either by describing the full system topology and describe what is
  in the same inner-shareable domain as the CPUs, which needs to
  encompass both DT and ACPI (starting with DT seems reasonable),

- or as a SoC specific erratum, but not as a general "sh*t happened"
  property.

AFAIK, Lorenzo is looking into this.

	M.

-- 
Without deviation from the norm, progress is not possible.