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Date:   Fri, 31 Mar 2023 19:14:45 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Swapnil Jakhade <sjakhade@cadence.com>
Cc:     kishon@kernel.org, linux-phy@lists.infradead.org,
        linux-kernel@vger.kernel.org, mparab@cadence.com, rogerq@kernel.org
Subject: Re: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink
 configuration
Message-ID: <ZCbjzXB3GW8siHYz@matsya>
References: <20230220141216.25326-1-sjakhade@cadence.com>
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On 20-02-23, 15:12, Swapnil Jakhade wrote:
> Add register sequences for PCIe + SGMII PHY multilink configuration.
> This has been validated on TI J7 platforms.

This fails to apply for me, can you please rebase

-- 
~Vinod