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Date:   Sat, 1 Apr 2023 22:21:24 +0800
From:   Xu Yilun <yilun.xu@intel.com>
To:     Nava kishore Manne <nava.kishore.manne@amd.com>
Cc:     mdf@kernel.org, hao.wu@intel.com, trix@redhat.com,
        michal.simek@xilinx.com, linux-fpga@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] fpga: zynq: Add parse_header ops support
Message-ID: <ZCg95G5P2KMnjTcr@yilunxu-OptiPlex-7050>
References: <20230327122057.205123-1-nava.kishore.manne@amd.com>
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In-Reply-To: <20230327122057.205123-1-nava.kishore.manne@amd.com>
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On 2023-03-27 at 17:50:57 +0530, Nava kishore Manne wrote:
> The commit 3cc624beba63 ("fpga: fpga-mgr: support bitstream offset in
> image buffer") added a new parse_header ops to handle the header related
> stuff in the fpga framework. So moved the header validation logic from
> write_init() to parse_header().

On second thought, I don't think the change is necessary. Implementing
parse_header only if the info->head/data_size needs runtime
re-evaluation according to the image. Otherwise, checking header in
write_init() is just fine.

Thanks,
Yilun

> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> ---
> Changes for v2:
>               - Limit the sync pattern validation size to header_size
>                 as suggested Yilun.
> 
> Changes for v3:
>               - zynq_fpga_has_sync () API is expecting "u8 *". So type cast
>                 formal parameter "const char *" to "u8 *".
> 
>  drivers/fpga/zynq-fpga.c | 23 ++++++++++++++++-------
>  1 file changed, 16 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index ae0da361e6c6..a6096f0c93fc 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -248,6 +248,21 @@ static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
>  	return false;
>  }
>  
> +static int zynq_fpga_ops_parse_header(struct fpga_manager *mgr,
> +				      struct fpga_image_info *info,
> +				      const char *buf, size_t count)
> +{
> +	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> +		if (!zynq_fpga_has_sync((u8 *)buf, info->header_size)) {
> +			dev_err(&mgr->dev,
> +				"Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
>  static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
>  				    struct fpga_image_info *info,
>  				    const char *buf, size_t count)
> @@ -275,13 +290,6 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
>  
>  	/* don't globally reset PL if we're doing partial reconfig */
>  	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> -		if (!zynq_fpga_has_sync(buf, count)) {
> -			dev_err(&mgr->dev,
> -				"Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n");
> -			err = -EINVAL;
> -			goto out_err;
> -		}
> -
>  		/* assert AXI interface resets */
>  		regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
>  			     FPGA_RST_ALL_MASK);
> @@ -545,6 +553,7 @@ static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr)
>  static const struct fpga_manager_ops zynq_fpga_ops = {
>  	.initial_header_size = 128,
>  	.state = zynq_fpga_ops_state,
> +	.parse_header = zynq_fpga_ops_parse_header,
>  	.write_init = zynq_fpga_ops_write_init,
>  	.write_sg = zynq_fpga_ops_write,
>  	.write_complete = zynq_fpga_ops_write_complete,
> -- 
> 2.25.1
>