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Date:   Mon, 3 Apr 2023 11:57:21 +0530
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Subject: Re: [PATCH net-next 2/2] net: ethernet: ti: am65-cpsw: Enable USXGMII
 mode for J784S4 CPSW9G
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To:     "Russell King (Oracle)" <linux@armlinux.org.uk>
References: <20230331065110.604516-1-s-vadapalli@ti.com>
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From:   Siddharth Vadapalli <s-vadapalli@ti.com>
In-Reply-To: <1477e0c3-bb92-72b0-9804-0393c34571d3@ti.com>
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Hello Russell,

On 31/03/23 19:16, Siddharth Vadapalli wrote:
> 
> 
> On 31-03-2023 16:42, Russell King (Oracle) wrote:
>> On Fri, Mar 31, 2023 at 04:23:16PM +0530, Siddharth Vadapalli wrote:
>>>
>>>
>>> On 31/03/23 15:16, Russell King (Oracle) wrote:
>>>> On Fri, Mar 31, 2023 at 02:55:56PM +0530, Siddharth Vadapalli wrote:
>>>>> Russell,
>>>>>
>>>>> On 31/03/23 13:54, Russell King (Oracle) wrote:
>>>>>> On Fri, Mar 31, 2023 at 01:35:10PM +0530, Siddharth Vadapalli wrote:
>>>>>>> Hello Russell,
>>>>>>>
>>>>>>> Thank you for reviewing the patch.
>>>>>>>
>>>>>>> On 31/03/23 13:27, Russell King (Oracle) wrote:
>>>>>>>> On Fri, Mar 31, 2023 at 12:21:10PM +0530, Siddharth Vadapalli wrote:
>>>>>>>>> TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the
>>>>>>>>> extra_modes member of the J784S4 SoC data. Additionally, configure the
>>>>>>>>> MAC Control register for supporting USXGMII mode. Also, for USXGMII
>>>>>>>>> mode, include MAC_5000FD in the "mac_capabilities" member of struct
>>>>>>>>> "phylink_config".
>>>>>>>>
>>>>>>>> I don't think TI "get" phylink at all...
>>>>>>>>
>>>>>>>>> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>>>>>>>>> index 4b4d06199b45..ab33e6fe5b1a 100644
>>>>>>>>> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>>>>>>>>> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>>>>>>>>> @@ -1555,6 +1555,8 @@ static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy
>>>>>>>>>  		mac_control |= CPSW_SL_CTL_GIG;
>>>>>>>>>  	if (interface == PHY_INTERFACE_MODE_SGMII)
>>>>>>>>>  		mac_control |= CPSW_SL_CTL_EXT_EN;
>>>>>>>>> +	if (interface == PHY_INTERFACE_MODE_USXGMII)
>>>>>>>>> +		mac_control |= CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN;
>>>>>>>>
>>>>>>>> The configuration of the interface mode should *not* happen in
>>>>>>>> mac_link_up(), but should happen in e.g. mac_config().
>>>>>>>
>>>>>>> I will move all the interface mode associated configurations to mac_config() in
>>>>>>> the v2 series.
>>>>>>
>>>>>> Looking at the whole of mac_link_up(), could you please describe what
>>>>>> effect these bits are having:
>>>>>>
>>>>>> 	CPSW_SL_CTL_GIG
>>>>>> 	CPSW_SL_CTL_EXT_EN
>>>>>> 	CPSW_SL_CTL_IFCTL_A
>>>>>
>>>>> CPSW_SL_CTL_GIG corresponds to enabling Gigabit mode (full duplex only).
>>>>> CPSW_SL_CTL_EXT_EN when set enables in-band mode of operation and when cleared
>>>>> enables forced mode of operation.
>>>>> CPSW_SL_CTL_IFCTL_A is used to set the RMII link speed (0=10 mbps, 1=100 mbps).
>>>>
>>>> Okay, so I would do in mac_link_up():
>>>>
>>>> 	/* RMII needs to be manually configured for 10/100Mbps */
>>>> 	if (interface == PHY_INTERFACE_MODE_RMII && speed == SPEED_100)
>>>> 		mac_control |= CPSW_SL_CTL_IFCTL_A;
>>>>
>>>> 	if (speed == SPEED_1000)
>>>> 		mac_control |= CPSW_SL_CTL_GIG;
>>>> 	if (duplex)
>>>> 		mac_control |= CPSW_SL_CTL_FULLDUPLEX;
>>>>
>>>> I would also make mac_link_up() do a read-modify-write operation to
>>>> only affect the bits that it is changing.
>>>
>>> This is the current implementation except for the SGMII mode associated
>>> operation that I had recently added. I will fix that. Also, the
>>> cpsw_sl_ctl_set() function which writes the mac_control value performs a read
>>> modify write operation.
>>>
>>>>
>>>> Now, for SGMII, I would move setting CPSW_SL_CTL_EXT_EN to mac_config()
>>>> to enable in-band mode - don't we want in-band mode enabled all the
>>>> time while in SGMII mode so the PHY gets the response from the MAC?
>>>
>>> Thank you for pointing it out. I will move that to mac_config().
>>>
>>>>
>>>> Lastly, for RGMII at 10Mbps, you seem to suggest that you need RGMII
>>>> in-band mode enabled for that - but if you need RGMII in-band for
>>>> 10Mbps, wouldn't it make sense for the other speeds as well? If so,
>>>> wouldn't that mean that CPSW_SL_CTL_EXT_EN can always be set for
>>>> RGMII no matter what speed is being used?
>>>
>>> The CPSW MAC does not support forced mode at 10 Mbps RGMII. For this reason, if
>>> RGMII 10 Mbps is requested, it is set to in-band mode.
>>
>> What I'm saying is that if we have in-band signalling that is reliable
>> for a particular interface mode, why not always use it, rather than
>> singling out one specific speed as an exception? Does it not work in
>> 100Mbps and 1Gbps?

While the CPSW MAC supports RGMII in-band status operation, the link partner
might not support it. I have also observed that forced mode is preferred to
in-band mode as implemented for another driver:
commit ade64eb5be9768e40c90ecb01295416abb2ddbac
net: dsa: microchip: Disable RGMII in-band status on KSZ9893

and in the mail thread at:
https://lore.kernel.org/netdev/20200905160647.GJ3164319@lunn.ch/
based on Andrew's suggestion, using forced mode appears to be better.

Additionally, I have verified that switching to in-band status causes a
regression. Thus, I will prefer keeping it in forced mode for 100 and 1000 Mbps
RGMII mode which is the existing implementation in the driver. Please let me know.

Regards,
Siddharth.

> 
> In-band RGMII is supported for speeds of 10, 100 and 1000 Mbps.
> Unfortunately, I am not aware of the reason why RGMII at speeds 100 and
> 1000 Mbps was implemented in the driver in forced mode. As suggested by
> you, I will work on implementing it in in-band mode for all speeds and
> verify that it works, following which I will post the v2 of this series,
> with the following changes based on your feedback:
> 1. All interface mode specific configuration will be moved to mac_config().
> 2. Since CPSW MAC supports USXGMII mode, MAC_5000FD will be added to the
> list of mac_capabilites unconditionally, unlike the current implementation.
> 3. In-band mode of operation will be enabled for all interface modes by
> default.
> 
> Regards,
> Siddharth.