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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 46cd0386-77cd-41dd-9696-08db34236ba0 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Apr 2023 09:11:33.6853 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fLL2MoRbz9eNTJ9iBnxR7s7QRXl3jjOtbxc5itW283AX48dP7yk/9mvEwi/0kozXRVzmvGszWHZlP4I+wXraVg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB7829 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: Re: gic700 shareability question >=20 > On Mon, Apr 03, 2023 at 01:36:31AM +0000, Peng Fan wrote: > > Hi Marc, > > > > > Subject: Re: gic700 shareability question > > > > > > + Lorenzo > > > > > > On Tue, 28 Mar 2023 13:48:19 +0100, > > > Peng Fan wrote: > > > > > > > > Hi Marc, > > > > > > > > We have an SoC that use GIC-700, but not support shareability, > > > > > > Define this. The IP does support shareability, but your integration > doesn't? > > > > > > > Currently I just hack the code as below. Do you think it is > > > > feasible to add firmware bindings such that these can be used to > > > > define the correct shareability/cacheability instead of relying on > > > > the programmability of the CBASER register? > > > > > > > > Saying with "broken-shareability", we just clear all the > > > > shareability settings. > > > > > > This is the same thing as the Rockchip crap, so you are in good compa= ny. > > > > > > I've repeatedly stated that this needs to be handled: > > > > > > - either by describing the full system topology and describe what is > > > in the same inner-shareable domain as the CPUs, which needs to > > > encompass both DT and ACPI (starting with DT seems reasonable), > > > > > > > We will give a look on this. But honestly not have a good idea on how. >=20 > It is a longer term fix for the issue, we are looking into this. >=20 > > > - or as a SoC specific erratum, but not as a general "sh*t happened" > > > property. > > > > I will ask the hardware team to create an errata. > > > > > > AFAIK, Lorenzo is looking into this. > > > > Lorenzo, are you working on this? >=20 > Yes it is being worked on, that does not prevent though an errata > workaround to be applied, firmware bindings definitions can take a while = to > sort out. Sure, we need go with errata. Thanks for working on this. Thanks, Peng. >=20 > Lorenzo