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Date:   Mon, 3 Apr 2023 17:21:27 +0100
From:   Conor Dooley <conor@kernel.org>
To:     =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= <bjorn@kernel.org>
Cc:     Albert Ou <aou@eecs.berkeley.edu>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        linux-riscv@lists.infradead.org,
        Guo Ren <guoren@linux.alibaba.com>,
        =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= <bjorn@rivosinc.com>,
        Heiko =?iso-8859-1?Q?St=FCbner?= <heiko@sntech.de>,
        Yipeng Zou <zouyipeng@huawei.com>,
        linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>,
        Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: Re: [PATCH] riscv: entry: Save a0 prior
 syscall_enter_from_user_mode()
Message-ID: <20230403-crisping-animosity-04ed8a45c625@spud>
References: <20230403065207.1070974-1-bjorn@kernel.org>
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On Mon, Apr 03, 2023 at 08:52:07AM +0200, Bj=F6rn T=F6pel wrote:
> From: Bj=F6rn T=F6pel <bjorn@rivosinc.com>
>=20
> The RISC-V calling convention passes the first argument, and the
> return value in the a0 register. For this reason, the a0 register
> needs some extra care; When handling syscalls, the a0 register is
> saved into regs->orig_a0, so a0 can be properly restored for,
> e.g. interrupted syscalls.
>=20
> This functionality was broken with the introduction of the generic
> entry patches. Here, a0 was saved into orig_a0 after calling
> syscall_enter_from_user_mode(), which can change regs->a0 for some
> paths, incorrectly restoring a0.
>=20
> This is resolved, by saving a0 prior doing the
> syscall_enter_from_user_mode() call.
>=20
> Fixes: f0bddf50586d ("riscv: entry: Convert to generic entry")
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Signed-off-by: Bj=F6rn T=F6pel <bjorn@rivosinc.com>

As you pointed out, v12 did indeed have this ordering, so *deep breath*
Reported-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/linux-riscv/60ee7c26-1a70-427d-beaf-92e2989fc=
479@spud/
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for fixing this Bj=F6rn!
> ---
>  arch/riscv/kernel/traps.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>=20
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index 1f4e37be7eb3..8c258b78c925 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -270,11 +270,11 @@ asmlinkage __visible __trap_section void do_trap_ec=
all_u(struct pt_regs *regs)
>  	if (user_mode(regs)) {
>  		ulong syscall =3D regs->a7;
> =20
> -		syscall =3D syscall_enter_from_user_mode(regs, syscall);
> -
>  		regs->epc +=3D 4;
>  		regs->orig_a0 =3D regs->a0;
> =20
> +		syscall =3D syscall_enter_from_user_mode(regs, syscall);
> +
>  		if (syscall < NR_syscalls)
>  			syscall_handler(regs, syscall);
>  		else
>=20
> base-commit: d34a6b715a23ccd9c9d0bc7a475bea59dc3e28b2
> --=20
> 2.37.2
>=20

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