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Message-ID: <357bb098-0c43-d4d6-8106-484492752e87@ti.com>
Date:   Tue, 4 Apr 2023 12:39:10 +0530
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CC:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <robh+dt@kernel.org>,
        <linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <srk@ti.com>,
        <s-vadapalli@ti.com>
Subject: Re: [PATCH] dt-bindings: phy: ti: phy-gmii-sel: Add support for
 J784S4 CPSW9G
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To:     <vkoul@kernel.org>, <kishon@kernel.org>
References: <20230315092408.1722114-1-s-vadapalli@ti.com>
 <921520a2-e3b5-7317-669f-a7c94895b34d@linaro.org>
From:   Siddharth Vadapalli <s-vadapalli@ti.com>
In-Reply-To: <921520a2-e3b5-7317-669f-a7c94895b34d@linaro.org>
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Hello Vinod,

Can this patch please be merged in case of no concerns?

Regards,
Siddharth.

On 19/03/23 18:15, Krzysztof Kozlowski wrote:
> On 15/03/2023 10:24, Siddharth Vadapalli wrote:
>> The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
>> additional PHY modes like QSGMII. Add a compatible for it.
>>
>> Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>>  Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 4 ++++
>>  1 file changed, 4 insertions(+)
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> Best regards,
> Krzysztof
>