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Date:   Tue, 4 Apr 2023 14:03:55 +0200
From:   Andrew Jones <ajones@ventanamicro.com>
To:     Anup Patel <anup@brainfault.org>
Cc:     Anup Patel <apatel@ventanamicro.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Atish Patra <atishp@atishpatra.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>, kvm@vger.kernel.org,
        kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 6/8] RISC-V: KVM: Add ONE_REG interface for AIA CSRs
Message-ID: <p3ifmb3r7g3soolhapkzlqyt5nq7ivb53w5fb5pp3274dd4ohp@whtjluacebeo>
References: <20230403093310.2271142-1-apatel@ventanamicro.com>
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On Tue, Apr 04, 2023 at 01:52:43PM +0200, Andrew Jones wrote:
> On Mon, Apr 03, 2023 at 02:23:01PM +0200, Andrew Jones wrote:
> > On Mon, Apr 03, 2023 at 05:34:57PM +0530, Anup Patel wrote:
> > > On Mon, Apr 3, 2023 at 5:01 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> > > >
> > > > On Mon, Apr 03, 2023 at 03:03:08PM +0530, Anup Patel wrote:
> > > > > We implement ONE_REG interface for AIA CSRs as a separate subtype
> > > > > under the CSR ONE_REG interface.
> > > > >
> > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > > > > ---
> > > > >  arch/riscv/include/uapi/asm/kvm.h | 8 ++++++++
> > > > >  arch/riscv/kvm/vcpu.c             | 8 ++++++++
> > > > >  2 files changed, 16 insertions(+)
> > > > >
> > > > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> > > > > index 182023dc9a51..cbc3e74fa670 100644
> > > > > --- a/arch/riscv/include/uapi/asm/kvm.h
> > > > > +++ b/arch/riscv/include/uapi/asm/kvm.h
> > > > > @@ -79,6 +79,10 @@ struct kvm_riscv_csr {
> > > > >       unsigned long scounteren;
> > > > >  };
> > > > >
> > > > > +/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> > > > > +struct kvm_riscv_aia_csr {
> > > > > +};
> > > > > +
> > > > >  /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> > > > >  struct kvm_riscv_timer {
> > > > >       __u64 frequency;
> > > > > @@ -107,6 +111,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> > > > >       KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
> > > > >       KVM_RISCV_ISA_EXT_ZICBOM,
> > > > >       KVM_RISCV_ISA_EXT_ZBB,
> > > >
> > > > Looks like this patch is also based on "[PATCH] RISC-V: KVM: Allow Zbb
> > > > extension for Guest/VM"
> > > 
> > > Yes, do you want me to change the order of dependency?
> > 
> > It's probably best if neither depend on each other, since they're
> > independent, but otherwise the order doesn't matter. It'd be nice to call
> > the order out in the cover letter to give patchwork a chance at automatic
> > build testing, though. To call it out, I believe adding
> > 
> > Based-on: 20230401112730.2105240-1-apatel@ventanamicro.com
> > 
> > to the cover letter should work.
> 
> I also just noticed that this based on "RISC-V: KVM: Add ONE_REG
> interface to enable/disable SBI extensions"[1] and it needs to be
> in order to pick up the KVM_REG_RISCV_SUBTYPE_MASK and
> KVM_REG_RISCV_SUBTYPE_SHIFT defines. It'd be good to call that
> patch out with Based-on.
> 
> [1]: 20230331174542.2067560-2-apatel@ventanamicro.com

And "RISC-V IPI Improvements",
20230328035223.1480939-1-apatel@ventanamicro.com, which is required
for riscv_get_intc_hwnode()

Thanks,
drew