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Date:   Tue, 4 Apr 2023 15:29:10 +0200
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Subject: Re: [PATCH v3 06/11] dt-bindings: PCI: Update the RK3399 example to a
 valid one
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To:     Rick Wertenbroek <rick.wertenbroek@gmail.com>
Cc:     alberto.dassatti@heig-vd.ch, damien.lemoal@opensource.wdc.com,
        xxm@rock-chips.com, Shawn Lin <shawn.lin@rock-chips.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= <kw@linux.com>,
        Rob Herring <robh@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Heiko Stuebner <heiko@sntech.de>,
        Johan Jonker <jbx6244@gmail.com>,
        Brian Norris <briannorris@chromium.org>,
        Caleb Connolly <kc@postmarketos.org>,
        Corentin Labbe <clabbe@baylibre.com>,
        Judy Hsiao <judyhsiao@chromium.org>,
        Lin Huang <hl@rock-chips.com>,
        Arnaud Ferraris <arnaud.ferraris@collabora.com>,
        Hugh Cole-Baker <sigmaris@gmail.com>,
        linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
References: <20230404082426.3880812-1-rick.wertenbroek@gmail.com>
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 <CAAEEuhrnp1QyP498V1wzyLv6KvfRCpNidF9NJpzg+kofWqrJtA@mail.gmail.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <CAAEEuhrnp1QyP498V1wzyLv6KvfRCpNidF9NJpzg+kofWqrJtA@mail.gmail.com>
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On 04/04/2023 10:58, Rick Wertenbroek wrote:
> On Tue, Apr 4, 2023 at 10:45 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 04/04/2023 10:24, Rick Wertenbroek wrote:
>>> Update the example in the documentation a valid example.
>>> The default max-outbound-regions is 32 but the example showed 16.
>>
>> This is not reason to be invalid. It is perfectly fine to change default
>> values to desired ones. What is not actually obvious is to change some
>> value to a default one, instead of removing it...
> 
> Hello, the example value <0x0 0x80000000 0x0 0x20000>; is plain wrong
> and will crash the kernel. This is a value that point to an address that falls
> in the DDR RAM region but depending on the amount of RAM on the
> board this address may not even exist (e.g., board with 2GB or less).

We talk about max-outbound-regions.

> 
> Also this address requires pointing to where the PCIe controller has the
> windows from AXI Physical space to PCIe space. This address is
> allocated when the SoC address map is created so it can only be that
> one unless rockchip refabs the SoC with another address map.
> 
> The example never worked with the values given as reported by e.g.,
> https://stackoverflow.com/questions/73586703/device-tree-issues-with-rockpro64-pcie-endpoint
> and here they set it to 0 (base of the DDR, which is a "valid" address
> as to it exists even on boards with less than 2GB) but it is still wrong
> to do so.

Again, my comment was under max-outbound-regions, not under some other
pieces. Does this all apply?

Best regards,
Krzysztof