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Wed, 5 Apr 2023 11:03:27 -0400 (EDT) Date: Wed, 5 Apr 2023 17:03:26 +0200 From: Maxime Ripard To: Roman Beranek Cc: Frank Oltmanns , Chen-Yu Tsai , David Airlie , Daniel Vetter , Jernej Skrabec , Samuel Holland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/sun4i: uncouple DSI dotclock divider from TCON0_DCLK_REG Message-ID: References: <20230320161636.24411-1-romanberanek@icloud.com> <87wn356ni4.fsf@oltmanns.dev> <20230327202045.ceeqqwjug4ktxtsf@penduick> <20230329195802.veybo3367zifw77n@penduick> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="3yjjmcpxi3qkranu" Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --3yjjmcpxi3qkranu Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Apr 05, 2023 at 02:34:11PM +0200, Roman Beranek wrote: > Hello Maxime, >=20 > On Wed Mar 29, 2023 at 9:58 PM CEST, Maxime Ripard wrote: > > > In order to preserve semantic correctness however, I propose to prefa= ce > > > the change with a patch that renames sun4i_dotclock and tcon-pixel-cl= ock > > > such that dot/pixel is replaced with d/data. What do you think? > > > > I don't think it's exposed to the userspace in any way so it makes sens= e to me > > >=20 > Here's a new series that includes those renames: > >=20 > It turns out however that the new dclk rates can't be set exactly as > requested without touching pll-video0*, tcon0 now therefore gets > reparented from pll-mipi to pll-video0-2x which, as it further turns > out, breaks DSI. While simply forbidding the video0-2x mux option seems > to me as the right way to go because there's not much use for it with > non-DSI interfaces either besides the opportunity to power pll-mipi > down, I'd like to run by you first. Sounds reasonable > * As pll-mipi doesn't have CLK_SET_RATE_PARENT flag set, pll-video0 > retains its boot-time rate of 294 MHz set by sunxi-dw-hdmi driver > in u-boot. Why 294 MHz (as opposed to the default rate of 297 MHz)? > The driver actually asks for 297 MHz, clock_set_pll3 rounds it to > 294 MHz though because it limits itself to 6 MHz steps. We could also address that though Maxime --3yjjmcpxi3qkranu Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCZC2NvgAKCRDj7w1vZxhR xbITAP9byIveCVVd6a8cqjY690IWR4pqo+XDDHeelvOTXcnloAEAoqs4t+zaupHu ywLZIz47coEFL0AyJr8kfHc1DcgKQQk= =6Dki -----END PGP SIGNATURE----- --3yjjmcpxi3qkranu--