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Date:   Thu, 6 Apr 2023 15:46:54 +0100
From:   Will Deacon <will@kernel.org>
To:     Mark Brown <broonie@kernel.org>
Cc:     Catalin Marinas <catalin.marinas@arm.com>,
        Joey Gouly <joey.gouly@arm.com>,
        Anshuman Khandual <anshuman.khandual@arm.com>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic
 generation
Message-ID: <20230406144653.GB11479@willie-the-truck>
References: <20230306-arm64-fgt-reg-gen-v3-0-decba93cbaab@kernel.org>
 <20230306-arm64-fgt-reg-gen-v3-2-decba93cbaab@kernel.org>
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On Thu, Mar 23, 2023 at 08:44:54PM +0000, Mark Brown wrote:
> Automatically generate the Hypervisor Fine-Grained Instruction Trap
> Register as per DDI0601 2022-12, currently we only have a definition for
> the register name not any of the contents.  No functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h |  1 -
>  arch/arm64/tools/sysreg         | 65 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 65 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index e5ca9ece1606..c48b41c9b0cc 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -419,7 +419,6 @@
>  #define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
>  #define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
>  #define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
> -#define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
>  #define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
>  
>  #define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 60829a9409f0..c06097a8b921 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -1941,6 +1941,71 @@ Sysreg HFGWTR_EL2	3	4	1	1	5
>  Fields	HFGxTR_EL2
>  EndSysreg
>  
> +Sysreg HFGITR_EL2	3	4	1	1	6
> +Res0	63:61
> +Field	60	COSPRCTX
> +Field	59	nGCSEPP
> +Field	58	nGCSSTR_EL1
> +Field	57	nGCSPUSHM_EL1

These aren't in the Arm ARM afaict ^^^

> +Field	56	nBRBIALL
> +Field	55	nBRBINJ
> +Field	54	DCCVAC
> +Field	53	SVC_EL1
> +Field	52	SVC_EL0
> +Field	51	ERET
> +Field	50	CPPRCTX
> +Field	49	DVPRCTX
> +Field	48	CFPRCTX
> +Field	47	TLBIVAALE1
> +Field	46	TLBIVALE1
> +Field	45	TLBIVAAE1
> +Field	44	TLBSIDE1

This is a typo ^^^

(I stopped reviewing at this point)

Can't we generate this file from the architecture xml? That would hopefully
avoid typos like this and make review less tedious.

Will