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From:   Jim Quinlan <jim2101024@gmail.com>
Date:   Thu, 6 Apr 2023 13:15:10 -0400
Message-ID: <CANCKTBspbkTXVBXTS+woymM+6kEgd+F5XH7ycPhaAgASEi7rhQ@mail.gmail.com>
Subject: Re: [PATCH v1 3/3] PCI: brcmstb: Allow setting the completion timeout
To:     Stefan Wahren <stefan.wahren@i2se.com>
Cc:     linux-pci@vger.kernel.org,
        Nicolas Saenz Julienne <nsaenz@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Cyril Brulebois <kibi@debian.org>,
        Phil Elwell <phil@raspberrypi.com>,
        bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com,
        Florian Fainelli <f.fainelli@gmail.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
        Rob Herring <robh@kernel.org>,
        "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" 
        <linux-rpi-kernel@lists.infradead.org>,
        "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>
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On Thu, Apr 6, 2023 at 11:59=E2=80=AFAM Stefan Wahren <stefan.wahren@i2se.c=
om> wrote:
>
> Hi Jim,
>
> Am 06.04.23 um 14:46 schrieb Jim Quinlan:
> > Since the STB PCIe HW will cause a CPU abort on a completion timeout ab=
ort,
> > we might as well extend the timeout limit.  Further, different devices =
and
> > systems may requires a larger or smaller amount for L1SS exit.
> >
> > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > ---
> >   drivers/pci/controller/pcie-brcmstb.c | 24 ++++++++++++++++++++++++
> >   1 file changed, 24 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/contro=
ller/pcie-brcmstb.c
> > index 129eee7bdbc1..92d78f4dfaae 100644
> > --- a/drivers/pci/controller/pcie-brcmstb.c
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -1080,6 +1080,29 @@ static void brcm_config_clkreq(struct brcm_pcie =
*pcie)
> >       writel(clkreq_set, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> >   }
> >
> > +static void brcm_config_completion_timeout(struct brcm_pcie *pcie)
> > +{
> > +     /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
> > +     const unsigned int REG_OFFSET =3D PCIE_RGR1_SW_INIT_1(pcie) - 8;
> > +     u32 timeout, timeout_msec =3D 1000;
> > +     u64 tmp64;
> > +     int ret;
> > +
> > +     ret =3D of_property_read_u32(pcie->np, "brcm,completion-abort-mse=
cs",
> > +                                &timeout_msec);
> > +
> > +     if (ret && ret !=3D -EINVAL)
> > +             dev_err(pcie->dev, "bad 'brcm,completion-abort-msecs' pro=
p\n");
>
> i'm not sure about the error behavior. If we want to proceed with
> defaults in such a case, i would make this a warning and mention the
> used defaults.
Will do.

>
> > +
> > +     /* Each unit in timeout register is 1/216,000,000 seconds */
> > +     tmp64 =3D (u64)216000 * timeout_msec;
> > +
> > +     /* Clamp the requested value before writing it */
> > +     timeout =3D tmp64 > 0xffffffff ? 0xffffffff : tmp64;
> > +     timeout =3D timeout < 0xffff ? 0xffff : timeout;
>
> Personally i'm not a huge fan of silently clamping wrong DT values.
I will add a warning with limit info  on clamp and have the YAML min+max.

Thanks
Jim Quinlan
Broadcom STB
>
> Best regards
>
> > +     writel(timeout, pcie->base + REG_OFFSET);
> > +}
> > +
> >   static int brcm_pcie_start_link(struct brcm_pcie *pcie)
> >   {
> >       struct device *dev =3D pcie->dev;
> > @@ -1110,6 +1133,7 @@ static int brcm_pcie_start_link(struct brcm_pcie =
*pcie)
> >               return -ENODEV;
> >       }
> >
> > +     brcm_config_completion_timeout(pcie);
> >       brcm_config_clkreq(pcie);
> >
> >       if (pcie->gen)