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From:   Linus Torvalds <torvalds@linux-foundation.org>
Date:   Thu, 6 Apr 2023 12:35:48 -0700
Message-ID: <CAHk-=whd4w2wu13O9b5VRKE1b3MoUk89Q_WzhELyqXGAKmfqmQ@mail.gmail.com>
Subject: Re: revert bab65e48cb064 PCI/MSI Sanitize MSI-X checks
To:     David Laight <David.Laight@aculab.com>
Cc:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Gunthorpe <jgg@nvidia.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Christoph Hellwig <hch@infradead.org>
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On Thu, Apr 6, 2023 at 4:05=E2=80=AFAM David Laight <David.Laight@aculab.co=
m> wrote:
>
> So code like:
>         for (i =3D 0; i < 16; i++)
>                 msix_tbl[i].entry =3D i;
>         nvec =3D pci_enable_msix_range(dev, msix_tbl, 1, 16);
> Now returns -22 if the hardware only supports 8 interrupts.
>
> Previously it returned 8.

Does just moving the pci_msix_validate_entries() down to below the
hwsize update code fix it?

IOW, something like this attached patch?

ENTIRELY UNTESTED! This may be seriously broken for some reason, but
it does seem like the current code makes no sense (that "Keep the IRQ
virtual hackery working" comment seems to not possibly be true since
the MSIX nvec has effectively been checked against hwsize by the
pci_msix_validate_entries() code before).

I don't know this code. Thomas?

                     Linus

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