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bh=7SImv1Rdk/+kE5EteKBqsurf3m5xVNf7BO/4yX5HUIM=; b=h+QGTud9MeU5Yo5c9uZz7C8AIEf+XI4qylLqgowFfuM9NHZRRTb5cWXw/uUAArAYI6 zVLpmtZEnOZG9NtlHyv979U4A36TWQb4xDSt1yWifHMT1mPXulLkkSJRran3uR6Ys/o0 4zevI/KvwzToVwKHKuSGu2nDVpybDygkg+PQ3y2iHvS3bokvpnboHTEsdLsUZHbS2Zdi CqbOx4LlIaZeY4zbkH+n14qNGAKcjIHdFqKVzsKk5vNEThv7ZJaIy732BgrmWh2AjRxt e1sNnxqXKht+rDR9Jizc+a2AGlAG+R+FJ0QufchqJfkWKXX46yuCqmShsY4vzxGlH6GM FGOQ== X-Gm-Message-State: AAQBX9dWiKfULaiHEd+9rJTPKsVqVDpOGQglxab+D3T35v76yb7XxfG4 RYRi0xMasOi/jBVRiUS4/6dlog== X-Received: by 2002:a05:6000:508:b0:2d7:89ce:8319 with SMTP id a8-20020a056000050800b002d789ce8319mr6475533wrf.27.1680811668794; Thu, 06 Apr 2023 13:07:48 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:4793:cb9a:340b:2f72]) by smtp.gmail.com with ESMTPSA id c11-20020adfe74b000000b002d89e113691sm2560506wrn.52.2023.04.06.13.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 13:07:48 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v2 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Date: Thu, 6 Apr 2023 22:07:16 +0200 Message-Id: <20230406200723.552644-1-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski Add the GPU and PCIe IOMMUs for sa8775p platforms as well as the required GPU clock controller driver. v1 -> v2: - remove unused include in the GPUCC driver - remove unused clock from the GPUCC driver and make it compatible with the generic QCom GPUCC bindings - put the new defconfig option in the right place (as per savedefconfig) and make the GPUCC driver a module rather than built-in - describe the smmu clocks for sa8775p in dt-bindings Bartosz Golaszewski (6): dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P arm64: defconfig: enable the SA8775P GPUCC driver dt-bindings: iommu: arm,smmu: enable clocks for sa8775p arm64: dts: qcom: sa8775p: add the pcie smmu node arm64: dts: qcom: sa8775p: add the GPU clock controller node arm64: dts: qcom: sa8775p: add the GPU IOMMU node Shazad Hussain (1): clk: qcom: add the GPUCC driver for sa8775p .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + .../devicetree/bindings/iommu/arm,smmu.yaml | 5 +- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 124 ++++ arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sa8775p.c | 625 ++++++++++++++++++ .../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 ++ 8 files changed, 814 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/qcom/gpucc-sa8775p.c create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h -- 2.37.2