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From:   Yazen Ghannam <yazen.ghannam@amd.com>
To:     <linux-i2c@vger.kernel.org>
CC:     <linux-kernel@vger.kernel.org>, <jdelvare@suse.com>,
        <terry.bowman@amd.com>, Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH] i2c: piix4: Print FCH::PM::S5_RESET_STATUS
Date:   Fri, 7 Apr 2023 15:37:20 -0500
Message-ID: <20230407203720.18184-1-yazen.ghannam@amd.com>
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The following register contains bits that indicate the cause for the
previous reset.

        PMx000000C0 (FCH::PM::S5_RESET_STATUS)

This is helpful for debug, etc., and it only needs to be read once from
a single FCH within the system. The register definition is AMD-specific.

Print it when the FCH MMIO space is first mapped. This register is not
related to I2C functionality, but read it here to leverage the existing
mapping.

Use an "info" log level so that it is printed every boot without requiring
the user to enable debug messages. This is beneficial when debugging
issues that cause spontaneous reboots and are hard to reproduce.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 drivers/i2c/busses/i2c-piix4.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index 809fbd014cd6..043b29f1e33c 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -100,6 +100,7 @@
 
 #define SB800_PIIX4_FCH_PM_ADDR			0xFED80300
 #define SB800_PIIX4_FCH_PM_SIZE			8
+#define SB800_PIIX4_FCH_PM_S5_RESET_STATUS	0xC0
 
 /* insmod parameters */
 
@@ -200,6 +201,9 @@ static int piix4_sb800_region_request(struct device *dev,
 
 		mmio_cfg->addr = addr;
 
+		addr += SB800_PIIX4_FCH_PM_S5_RESET_STATUS;
+		pr_info_once("S5_RESET_STATUS = 0x%08x", ioread32(addr));
+
 		return 0;
 	}
 
-- 
2.34.1