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Howlett" Subject: [PATCH v2 2/3] genirq: Encapsulate sparse bitmap handling Date: Sat, 8 Apr 2023 12:15:25 -0500 Message-ID: <20230408171526.3059039-3-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230408171526.3059039-1-sdonthineni@nvidia.com> References: <20230408171526.3059039-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT085:EE_|SA3PR12MB7857:EE_ X-MS-Office365-Filtering-Correlation-Id: 047281f5-dee2-461e-40f5-08db3854db70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uKvmiux4rl3vsnm92UoRs8n5/OpWhCUYkJSZ9ngDkxECtiZdXQD1cI3KB5xaBaoR/SjTjq6D5zQuPk8kipMKA5Cqe53/mKLJ+EFLqmeK0WPyi/0Kivzc+V7GqZcD7HQIO7PkxchaN/McpOYF30+sWr8y6VIXbl8HDqrWILhgapIUPCc6Zs62dDlS8MUfC6ZQALMbs9sZRZUT6H/ihgMZtwUXo9o53w9TEYr6xxfIwpB3S3V39ZugbLCz78RnbCkEX3OCp3oWU7HJ8PWnAffY0fjedQGTaLTq5F/7VtFtceDFUGGjiwIeXm0Tu9mDhW79z8db0t7k9DqrTO2r56JFnB9q+KZT5wV4eB0fpvvqKgI1aDqmPF40ub5ue+IKu2gM8UtizQt2mMwzIwjLylTfMASKmugVgVxkLZhrFiGQ9AlLCIIl9HHHh6jUwWqvNu5oCvn0SXxNlgdxGRu8fCfKoBd7BFBub8EaGQVl0XBi+tEQIGUgg0VVJXvH7/7LCyNt2b6OHYoOWxy8mFYP05+6d3M7ApWHQF0WG6Ci/Qn1/YlsHWKEQJH/GdNwIAHwXCvpZURQSYdAawFT1I8EhItCGwm/yS/lAc2QQVkJ2y1L8As6ZmLsmU20j5AeyFvWdoibkrYOdQUIYFwrrGcBwKWm0KmSmhp8fMMw/VeUj96gtilfPwlPTZvRKfYqrS50Sk3XUM/28pUBd76SB75FQuXK1s42eXM5RXaYQkTVYSbizUQ= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199021)(46966006)(36840700001)(7696005)(478600001)(86362001)(40480700001)(47076005)(83380400001)(36756003)(82740400003)(7636003)(356005)(2616005)(36860700001)(426003)(336012)(6666004)(2906002)(54906003)(110136005)(316002)(186003)(1076003)(26005)(8676002)(41300700001)(8936002)(5660300002)(82310400005)(4326008)(70586007)(70206006);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2023 17:15:31.2095 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 047281f5-dee2-461e-40f5-08db3854db70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7857 X-Spam-Status: No, score=0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move the open coded sparse bitmap handling into helper functions as a preparatory step for converting the sparse interrupt management to a maple tree. No functional change. Signed-off-by: Shanker Donthineni --- kernel/irq/internals.h | 4 ++-- kernel/irq/irqdesc.c | 28 +++++++++++++++++++--------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 2fd17057ed4b..5d741b0e7d5e 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,9 +12,9 @@ #include #ifdef CONFIG_SPARSE_IRQ -# define IRQ_BITMAP_BITS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS (NR_IRQS + 8196) #else -# define IRQ_BITMAP_BITS NR_IRQS +# define MAX_SPARSE_IRQS NR_IRQS #endif #define istate core_internal_state__do_not_mess_with_it diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 47543b5a0edb..e0c259769d3a 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -131,7 +131,18 @@ int nr_irqs = NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); +static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); + +static int irq_find_free_area(unsigned int from, unsigned int cnt) +{ + return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, + from, cnt, 0); +} + +static unsigned int irq_find_next_irq(unsigned int offset) +{ + return find_next_bit(allocated_irqs, nr_irqs, offset); +} #ifdef CONFIG_SPARSE_IRQ @@ -519,7 +530,7 @@ static int alloc_descs(unsigned int start, unsigned int cnt, int node, static int irq_expand_nr_irqs(unsigned int nr) { - if (nr > IRQ_BITMAP_BITS) + if (nr > MAX_SPARSE_IRQS) return -ENOMEM; nr_irqs = nr; return 0; @@ -537,11 +548,11 @@ int __init early_irq_init(void) printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n", NR_IRQS, nr_irqs, initcnt); - if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) - nr_irqs = IRQ_BITMAP_BITS; + if (WARN_ON(nr_irqs > MAX_SPARSE_IRQS)) + nr_irqs = MAX_SPARSE_IRQS; - if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) - initcnt = IRQ_BITMAP_BITS; + if (WARN_ON(initcnt > MAX_SPARSE_IRQS)) + initcnt = MAX_SPARSE_IRQS; if (initcnt > nr_irqs) nr_irqs = initcnt; @@ -816,8 +827,7 @@ __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, mutex_lock(&sparse_irq_lock); - start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS, - from, cnt, 0); + start = irq_find_free_area(from, cnt); ret = -EEXIST; if (irq >=0 && start != irq) goto unlock; @@ -842,7 +852,7 @@ EXPORT_SYMBOL_GPL(__irq_alloc_descs); */ unsigned int irq_get_next_irq(unsigned int offset) { - return find_next_bit(allocated_irqs, nr_irqs, offset); + return irq_find_next_irq(offset); } struct irq_desc * -- 2.25.1