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Date:   Tue, 11 Apr 2023 10:06:06 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Mason Huo <mason.huo@starfivetech.com>
CC:     "Rafael J. Wysocki" <rafael@kernel.org>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Shengyu Qu <wiagn233@outlook.com>, <linux-pm@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110
 SoC
Message-ID: <20230411-darling-chump-faaf8dec29ef@wendy>
References: <20230411083257.16155-1-mason.huo@starfivetech.com>
 <20230411083257.16155-4-mason.huo@starfivetech.com>
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Hey Mason,

On Tue, Apr 11, 2023 at 04:32:57PM +0800, Mason Huo wrote:
> Add the operating-points-v2 to support cpu scaling
> on StarFive JH7110 SoC.

(btw, there's no need to wrap commit messages at 52 columns, you have
72 to work with)

> It supports up to 4 cpu frequency loads.
>=20
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
>  .../jh7110-starfive-visionfive-2.dtsi         | 25 +++++++++++++++++++
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 25 +++++++++++++++++++
>  2 files changed, 50 insertions(+)
>=20
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dt=
si b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index df582bddae4b..ae446b268e78 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -228,3 +228,28 @@ &uart0 {
>  	pinctrl-0 =3D <&uart0_pins>;
>  	status =3D "okay";
>  };
> +
> +&U74_1 {
> +	clocks =3D  <&syscrg JH7110_SYSCLK_CPU_CORE>;
> +	clock-names =3D "cpu";
> +	cpu-supply =3D <&reg_dcdc2>;
> +};
> +
> +&U74_2 {
> +	clocks =3D  <&syscrg JH7110_SYSCLK_CPU_CORE>;
> +	clock-names =3D "cpu";
> +	cpu-supply =3D <&reg_dcdc2>;
> +};
> +
> +&U74_3 {
> +	clocks =3D  <&syscrg JH7110_SYSCLK_CPU_CORE>;
> +	clock-names =3D "cpu";
> +	cpu-supply =3D <&reg_dcdc2>;
> +};
> +
> +&U74_4 {
> +	clocks =3D  <&syscrg JH7110_SYSCLK_CPU_CORE>;
                ^^
There's a double space in each of these.

> +	clock-names =3D "cpu";
> +	cpu-supply =3D <&reg_dcdc2>;
> +};

How come these two clock properties are being added in <board>.dtsi?
Should they not be in <soc>.dtsi?

Thanks,
Conor.

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZDUi/gAKCRB4tDGHoIJi
0nEZAP9rj/CuBXvNfE91n2hagQY3313ZTlg0J0xHWjSonAhoBwD/cwrCXvzzmaqL
aVdM9JA8ul3lc3HBxlANw2iL7G3eWAI=
=Ix5Y
-----END PGP SIGNATURE-----

--9RmMYoUwAG4qQ11d--