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Date:   Tue, 11 Apr 2023 22:35:04 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Hal Feng <hal.feng@starfivetech.com>
Cc:     linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org,
        Conor Dooley <conor.dooley@microchip.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Ben Dooks <ben.dooks@sifive.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 00/22] Basic clock, reset & device tree support for
 StarFive JH7110 RISC-V SoC
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References: <20230401111934.130844-1-hal.feng@starfivetech.com>
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On Thu, Apr 06, 2023 at 03:03:14PM +0800, Hal Feng wrote:
> On Wed,  5 Apr 2023 22:30:45 +0100, Conor Dooley wrote:

> > Hal, can you get your folks to resend whatever dts bits that are now
> > applicable? IOW, the dt-bindings for the entries are in a for-next
> > branch for some subsystem.
>=20
> Of course. As far as I know, these nodes include trng / pmu / mmc / qspi.

Just FYI, you can get the lads to resend them whenever, but it's too
late for v6.4 now.

Cheers,
Conor.


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