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Message-ID: <91855baa-88cb-96b1-d571-4881ea6d24c8@starfivetech.com>
Date:   Wed, 12 Apr 2023 10:12:44 +0800
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Subject: Re: [PATCH v7 00/22] Basic clock, reset & device tree support for
 StarFive JH7110 RISC-V SoC
To:     Conor Dooley <conor@kernel.org>
CC:     <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>,
        Conor Dooley <conor.dooley@microchip.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Ben Dooks <ben.dooks@sifive.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        "Marc Zyngier" <maz@kernel.org>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        <linux-kernel@vger.kernel.org>
References: <20230401111934.130844-1-hal.feng@starfivetech.com>
 <20230405-wharf-rejoin-5222e5958611@spud>
 <ce311dcf-67a5-bf15-d0da-88967baf4ee9@starfivetech.com>
 <20230411-gleaming-parasail-34e2b7c3de2e@spud>
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From:   Hal Feng <hal.feng@starfivetech.com>
In-Reply-To: <20230411-gleaming-parasail-34e2b7c3de2e@spud>
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On Tue, 11 Apr 2023 22:35:04 +0100, Conor Dooley wrote:
> On Thu, Apr 06, 2023 at 03:03:14PM +0800, Hal Feng wrote:
>> On Wed,  5 Apr 2023 22:30:45 +0100, Conor Dooley wrote:
> 
>> > Hal, can you get your folks to resend whatever dts bits that are now
>> > applicable? IOW, the dt-bindings for the entries are in a for-next
>> > branch for some subsystem.
>> 
>> Of course. As far as I know, these nodes include trng / pmu / mmc / qspi.
> 
> Just FYI, you can get the lads to resend them whenever, but it's too
> late for v6.4 now.

I knew it later that, trng depends on stg clock dt-bindings, mmc depends on
syscon dt-bindings which will be merged into the pll clock driver, the
dt-bindings of qspi need to be fixed due to the actual number of clock
inputs it need is 3. Walker plans to resend the pmu bits these days, but
sorry to hear that it's too late now.

Best regards,
Hal