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([2a02:810d:15c0:828:8fa0:9989:3f72:b14f]) by smtp.gmail.com with ESMTPSA id tg12-20020a1709078dcc00b0094a473988b9sm4173113ejc.27.2023.04.12.01.35.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Apr 2023 01:35:07 -0700 (PDT) Message-ID: Date: Wed, 12 Apr 2023 10:35:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v1 1/7] dt-bindings: power: Constrain properties for JH7110 PMU Content-Language: en-US To: Changhuang Liang , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Walker Chen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> <20230411064743.273388-2-changhuang.liang@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <20230411064743.273388-2-changhuang.liang@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/04/2023 08:47, Changhuang Liang wrote: > When use "starfive,jh7110-pmu-dphy" compatible, do not need the reg and > interrupts properties. > > Signed-off-by: Changhuang Liang > --- > .../bindings/power/starfive,jh7110-pmu.yaml | 14 ++++++++++++-- > include/dt-bindings/power/starfive,jh7110-pmu.h | 3 +++ > 2 files changed, 15 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml > index 98eb8b4110e7..ffb4406c2e56 100644 > --- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml > +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml > @@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit > > maintainers: > - Walker Chen > + - Changhuang Liang > > description: | > StarFive JH7110 SoC includes support for multiple power domains which can be > @@ -17,6 +18,7 @@ properties: > compatible: > enum: > - starfive,jh7110-pmu > + - starfive,jh7110-pmu-dphy You do here much more than commit msg says. Isn'y DPHY a phy? Why is it in power? > > reg: > maxItems: 1 > @@ -29,10 +31,18 @@ properties: > > required: > - compatible > - - reg > - - interrupts > - "#power-domain-cells" > > +if: Put it under allOf (in this place). Will save you one re-indentation later. > + properties: > + compatible: > + contains: > + const: starfive,jh7110-pmu > +then: > + required: > + - reg > + - interrupts > + > additionalProperties: false > > examples: > diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h > index 132bfe401fc8..0bfd6700c144 100644 > --- a/include/dt-bindings/power/starfive,jh7110-pmu.h > +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h > @@ -14,4 +14,7 @@ > #define JH7110_PD_ISP 5 > #define JH7110_PD_VENC 6 > > +#define JH7110_PD_DPHY_TX 0 > +#define JH7110_PD_DPHY_RX 1 > + > #endif Best regards, Krzysztof