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Date:   Thu, 13 Apr 2023 08:06:23 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Conor Dooley <conor@kernel.org>,
        Prabhakar <prabhakar.csengg@gmail.com>
CC:     Prabhakar <prabhakar.csengg@gmail.com>,
        Arnd Bergmann <arnd@arndb.de>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
        Andrew Jones <ajones@ventanamicro.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Samuel Holland <samuel@sholland.org>,
        <linux-riscv@lists.infradead.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-renesas-soc@vger.kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP
 RISC-V core
Message-ID: <20230413-aorta-unheated-c9bb35411fb2@wendy>
References: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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On Wed, Apr 12, 2023 at 09:25:34PM +0100, Conor Dooley wrote:
> On Wed, Apr 12, 2023 at 12:08:58PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >=20
> > I/O Coherence Port (IOCP) provides an AXI interface for connecting
> > external non-caching masters, such as DMA controllers. The accesses
> > from IOCP are coherent with D-Caches and L2 Cache.
> >=20
> > IOCP is a specification option and is disabled on the Renesas RZ/Five
> > SoC due to this reason IP blocks using DMA will fail.
> >=20
> > The Andes AX45MP core has a Programmable Physical Memory Attributes (PM=
A)
> > block that allows dynamic adjustment of memory attributes in the runtim=
e.
> > It contains a configurable amount of PMA entries implemented as CSR
> > registers to control the attributes of memory locations in interest.
> > Below are the memory attributes supported:
> > * Device, Non-bufferable
> > * Device, bufferable
> > * Memory, Non-cacheable, Non-bufferable
> > * Memory, Non-cacheable, Bufferable
> > * Memory, Write-back, No-allocate
> > * Memory, Write-back, Read-allocate
> > * Memory, Write-back, Write-allocate
> > * Memory, Write-back, Read and Write-allocate
> >=20
> > More info about PMA (section 10.3):
> > Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-=
Datasheet.pdf
> >=20
> > As a workaround for SoCs with IOCP disabled CMO needs to be handled by
> > software. Firstly OpenSBI configures the memory region as
> > "Memory, Non-cacheable, Bufferable" and passes this region as a global
> > shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
> > allocations happen from this region and synchronization callbacks are
> > implemented to synchronize when doing DMA transactions.
> >=20
> > Example PMA region passes as a DT node from OpenSBI:
> >     reserved-memory {
> >         #address-cells =3D <2>;
> >         #size-cells =3D <2>;
> >         ranges;
> >=20
> >         pma_resv0@58000000 {
> >             compatible =3D "shared-dma-pool";
> >             reg =3D <0x0 0x58000000 0x0 0x08000000>;
> >             no-map;
> >             linux,dma-default;
> >         };
> >     };
> >=20
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v7 -> v8
> > * Dropped function pointer usage
> > * Now exporting the functions for clean/inval/flush
> > * Switched to using early_initcall instead of arch_initcall
> > * Dropped entry for "include/cache" from MAINTAINERS
> > * Dropped dependency of RISCV on AX45MP_L2_CACHE
> > * Returning error in case of cache line mismatch
>=20
> > * Renamed clean/inval/flush functions
>=20
> I kinda screwed you with that request given Hellwig's NAK on the
> function pointer based stuff. Ah well, I prefer matching the proposed
> naming of the dma core to what RVI chose for the instructions.
>=20
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>=20
> I suppose this will need a resubmission once Arnd's stuff gets applied,
> but I would like to see it have a run through the build bots etc.

So apparently my build bot did actually run against this series?
https://patchwork.kernel.org/project/linux-riscv/list/?series=3D739109

To be quite honest, I am not sure at all how it managed to apply the
series w/ Arnd's pre-reqs. Perhaps it has achieved some from of
sentience. There's a build failure for 32-bit that appeared on the final
patch, but is not really its fault:
=2E./arch/riscv/mm/dma-noncoherent.c: Assembler messages:
=2E./arch/riscv/mm/dma-noncoherent.c:104: Error: unrecognized opcode `sd s0=
,0(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:105: Error: unrecognized opcode `sd ra=
,8(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:110: Error: unrecognized opcode `ld ra=
,8(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:111: Error: unrecognized opcode `ld s0=
,0(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:111: Error: unrecognized opcode `sd s0=
,0(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:112: Error: unrecognized opcode `sd ra=
,8(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:117: Error: unrecognized opcode `ld ra=
,8(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:118: Error: unrecognized opcode `ld s0=
,0(sp)'
=2E./arch/riscv/mm/pmem.c: Assembler messages:
=2E./arch/riscv/mm/pmem.c:98: Error: unrecognized opcode `sd s0,0(sp)'
=2E./arch/riscv/mm/pmem.c:99: Error: unrecognized opcode `sd ra,8(sp)'
=2E./arch/riscv/mm/pmem.c:104: Error: unrecognized opcode `ld ra,8(sp)'
=2E./arch/riscv/mm/pmem.c:105: Error: unrecognized opcode `ld s0,0(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:138: Error: unrecognized opcode `sd s0=
,0(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:139: Error: unrecognized opcode `sd ra=
,8(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:144: Error: unrecognized opcode `ld ra=
,8(sp)'
=2E./arch/riscv/mm/dma-noncoherent.c:145: Error: unrecognized opcode `ld s0=
,0(sp)'
=2E./arch/riscv/mm/pmem.c:104: Error: unrecognized opcode `sd s0,0(sp)'
=2E./arch/riscv/mm/pmem.c:105: Error: unrecognized opcode `sd ra,8(sp)'
=2E./arch/riscv/mm/pmem.c:110: Error: unrecognized opcode `ld ra,8(sp)'
=2E./arch/riscv/mm/pmem.c:111: Error: unrecognized opcode `ld s0,0(sp)'
=2E./arch/riscv/mm/pmem.c:110: Error: attempt to move .org backwards
=2E./arch/riscv/mm/pmem.c:116: Error: attempt to move .org backwards
=2E./arch/riscv/mm/dma-noncoherent.c:116: Error: attempt to move .org backw=
ards
=2E./arch/riscv/mm/dma-noncoherent.c:123: Error: attempt to move .org backw=
ards
=2E./arch/riscv/mm/dma-noncoherent.c:150: Error: attempt to move .org backw=
ards
make[4]: *** [../scripts/Makefile.build:252: arch/riscv/mm/pmem.o] Error 1
make[4]: *** [../scripts/Makefile.build:252: arch/riscv/mm/dma-noncoherent.=
o] Error 1
make[4]: Target 'arch/riscv/mm/' not remade because of errors.
make[3]: *** [../scripts/Makefile.build:494: arch/riscv/mm] Error 2
make[3]: Target 'arch/riscv/' not remade because of errors.
make[2]: *** [../scripts/Makefile.build:494: arch/riscv] Error 2

The simplest solution may to just be making the erratum depend on 64BIT?

Cheers,
Conor.


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