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([2a02:810d:15c0:828:ec6f:1b33:ab3f:bfd7]) by smtp.gmail.com with ESMTPSA id k13-20020a17090632cd00b0094e96e46cc0sm636865ejk.69.2023.04.13.01.41.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Apr 2023 01:41:24 -0700 (PDT) Message-ID: Date: Thu, 13 Apr 2023 10:41:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v4 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx Content-Language: en-US To: Changhuang Liang , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel Cc: Jack Zhu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org References: <20230412084540.295411-1-changhuang.liang@starfivetech.com> <20230412084540.295411-2-changhuang.liang@starfivetech.com> <8dd0dc63-e0df-8764-f756-da032d9d671c@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/04/2023 04:34, Changhuang Liang wrote: >>>>> + lane_maps: >>>> >>>> Why did this appear? Underscores are not allowed. It looks like you >>>> re-implement some standard property. >>>> >>> >>> Will change to lane-maps. >>> Yes, according to Vinod advice, lane mapping table use device tree >>> to parse makes sense. >> >> Hm, I have a feeling that I saw such property, so you should dig into >> existing and in-flight bindings. >> >> Best regards, >> Krzysztof >> > > A standard property? Like "clocks" or "resets"? Like lane-polarities now submitted to one MIPI. Anyway it does not look like a property of a board. You said it is fixed per SoC, so it should be implied from the compatible. Otherwise please explain in description and provide some rationale. Best regards, Krzysztof