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From:   "Potthuri, Sai Krishna" <sai.krishna.potthuri@amd.com>
To:     Mark Brown <broonie@kernel.org>
CC:     "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "git (AMD-Xilinx)" <git@amd.com>,
        "saikrishna12468@gmail.com" <saikrishna12468@gmail.com>
Subject: RE: [PATCH 0/2] spi: cadence-quadspi: Fix random issues with Xilinx
 Versal DMA read
Thread-Topic: [PATCH 0/2] spi: cadence-quadspi: Fix random issues with Xilinx
 Versal DMA read
Thread-Index: AQHZWxM2HYB0zugnmUSUtTuM77veuq8qd2Bg
Date:   Fri, 14 Apr 2023 06:05:15 +0000
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References: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com>
In-Reply-To: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com>
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> -----Original Message-----
> From: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Sent: Monday, March 20, 2023 3:29 PM
> To: Mark Brown <broonie@kernel.org>
> Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; git (AMD-Xil=
inx)
> <git@amd.com>; saikrishna12468@gmail.com; Potthuri, Sai Krishna
> <sai.krishna.potthuri@amd.com>
> Subject: [PATCH 0/2] spi: cadence-quadspi: Fix random issues with Xilinx =
Versal
> DMA read
>=20
> Update Xilinx Versal external DMA read logic to fix random issues
> - Instead of having the fixed timeout, update the read timeout based on t=
he
> length of the transfer to avoid timeout for larger data size.
> - While switching between external DMA read and indirect read, disable th=
e SPI
> before configuration and enable it after configuration as recommended by =
Octal-
> SPI Flash Controller specification.
>=20
> Sai Krishna Potthuri (2):
>   spi: cadence-quadspi: Update the read timeout based on the length
>   spi: cadence-quadspi: Disable the SPI before reconfiguring
>=20
>  drivers/spi/spi-cadence-quadspi.c | 40 ++++++++++++++++++-------------
>  1 file changed, 24 insertions(+), 16 deletions(-)
>=20
> --
Mark: Do you have any comments on this series?

Regards
Sai Krishna