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Message-ID: <2a05dac0-c57e-a3cd-ec4d-55cf32e6dce9@arm.com>
Date:   Fri, 14 Apr 2023 10:19:56 +0200
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Subject: Re: [PATCH v3 2/4] cacheinfo: Check cache properties are present in
 DT
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To:     Florian Fainelli <f.fainelli@gmail.com>,
        linux-kernel@vger.kernel.org
Cc:     Radu Rendec <rrendec@redhat.com>,
        Alexandre Ghiti <alexghiti@rivosinc.com>,
        Conor Dooley <conor.dooley@microchip.com>,
        Will Deacon <will@kernel.org>,
        Sudeep Holla <sudeep.holla@arm.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        "Rafael J. Wysocki" <rafael@kernel.org>,
        Palmer Dabbelt <palmer@rivosinc.com>,
        Gavin Shan <gshan@redhat.com>
References: <20230413091436.230134-1-pierre.gondois@arm.com>
 <20230413091436.230134-3-pierre.gondois@arm.com>
 <4da53918-839b-4d28-0634-66fd7f38c8bd@gmail.com>
From:   Pierre Gondois <pierre.gondois@arm.com>
In-Reply-To: <4da53918-839b-4d28-0634-66fd7f38c8bd@gmail.com>
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Hello Florian,

On 4/13/23 20:16, Florian Fainelli wrote:
> On 4/13/23 02:14, Pierre Gondois wrote:
>> If a Device Tree (DT) is used, the presence of cache properties is
>> assumed. Not finding any is not considered. For arm64 platforms,
>> cache information can be fetched from the clidr_el1 register.
>> Checking whether cache information is available in the DT
>> allows to switch to using clidr_el1.
>>
>> init_of_cache_level()
>> \-of_count_cache_leaves()
>> will assume there a 2 cache leaves (L1 data/instruction caches), which
>> can be different from clidr_el1 information.
>>
>> cache_setup_of_node() tries to read cache properties in the DT.
>> If there are none, this is considered a success. Knowing no
>> information was available would allow to switch to using clidr_el1.
>>
>> Fixes: de0df442ee49 ("cacheinfo: Check 'cache-unified' property to count cache leaves")
>> Reported-by: Alexandre Ghiti <alexghiti@rivosinc.com>
>> Link: https://lore.kernel.org/all/20230404-hatred-swimmer-6fecdf33b57a@spud/
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> 
> Humm, it would appear that the cache levels and topology is still
> provided, despite the lack of cache properties in the Device Tree which
> is intended by this patch set however we lost the size/ways/sets
> information, could we not complement the missing properties here?
> 
> If this is out of the scope of what you are doing:
> 
> Tested-by: Florian Fainelli <f.fainelli@gmail.com>

I submitted a v4 at:
https://lore.kernel.org/all/20230414081453.244787-1-pierre.gondois@arm.com/

I haven't included your Tested-by as there were some small changes.
If you consider these changes are small enough to include your tag,
please let know,

Regards,
Pierre