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From:   Adam Ford <aford173@gmail.com>
To:     dri-devel@lists.freedesktop.org
Cc:     m.szyprowski@samsung.com, marex@denx.de, aford@beaconembedded.com,
        Adam Ford <aford173@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Inki Dae <inki.dae@samsung.com>,
        Jagan Teki <jagan@amarulasolutions.com>,
        Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Robert Foss <rfoss@kernel.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/6] drm: bridge: samsung-dsim: Support multi-lane calculations
Date:   Sat, 15 Apr 2023 05:40:58 -0500
Message-Id: <20230415104104.5537-1-aford173@gmail.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

If there is more than one lane, the HFP, HBP, and HSA is calculated in
bytes/pixel, then they are divided amongst the different lanes with some
additional overhead. This is necessary to achieve higher resolutions while
keeping the pixel clocks lower as the number of lanes increase.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 40 +++++++++++++++++++++++----
 1 file changed, 34 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..1ccbad4ea577 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -215,6 +215,7 @@
 #define DSI_RX_FIFO_SIZE		256
 #define DSI_XFER_TIMEOUT_MS		100
 #define DSI_RX_FIFO_EMPTY		0x30800002
+#define DSI_HSYNC_PKT_OVERHEAD	6
 
 #define OLD_SCLK_MIPI_CLK_NAME		"pll_clk"
 
@@ -879,13 +880,40 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
 			| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
 		samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
 
-		reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
-			| DSIM_MAIN_HBP(m->htotal - m->hsync_end);
-		samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
+		/*
+		 * If there is more than one lane, the HFP, HBP, and HSA
+		 * is calculated in bytes/pixel, then they are divided
+		 * amongst the different lanes with some additional
+		 * overhead correction
+		 */
+		if (dsi->lanes > 1) {
+			u32 hfp, hbp, hsa;
+			int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format) / 8;
+
+			hfp = ((m->hsync_start - m->hdisplay) * bpp) / dsi->lanes;
+			hfp -= (hfp > DSI_HSYNC_PKT_OVERHEAD) ? DSI_HSYNC_PKT_OVERHEAD : 0;
+
+			hbp = ((m->htotal - m->hsync_end) * bpp) / dsi->lanes;
+			hbp -= (hbp > DSI_HSYNC_PKT_OVERHEAD) ? DSI_HSYNC_PKT_OVERHEAD : 0;
 
-		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
-			| DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
-		samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
+			hsa = ((m->hsync_end - m->hsync_start) * bpp) / dsi->lanes;
+			hsa -= (hsa > DSI_HSYNC_PKT_OVERHEAD) ? DSI_HSYNC_PKT_OVERHEAD : 0;
+
+			reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
+			samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
+
+			reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
+				| DSIM_MAIN_HSA(hsa);
+			samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
+		} else {
+			reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
+				| DSIM_MAIN_HBP(m->htotal - m->hsync_end);
+			samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
+
+			reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
+				| DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
+			samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
+		}
 	}
 	reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
 		DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
-- 
2.39.2