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charset=us-ascii Content-Disposition: inline In-Reply-To: <20230302124015.75546-2-y.oudjana@protonmail.com> X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 02, 2023 at 03:40:14PM +0300, Yassine Oudjana wrote: > From: Yassine Oudjana > > Add a DT binding for the MT6735 top reset generation unit/watchdog timer. > > Signed-off-by: Yassine Oudjana > Reviewed-by: AngeloGioacchino Del Regno > Reviewed-by: Krzysztof Kozlowski Reviewed-by: Guenter Roeck > --- > .../bindings/watchdog/mediatek,mtk-wdt.yaml | 1 + > include/dt-bindings/reset/mediatek,mt6735-wdt.h | 17 +++++++++++++++++ > 2 files changed, 18 insertions(+) > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-wdt.h > > diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml > index 55b34461df1b..009ccdb60b84 100644 > --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml > +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml > @@ -22,6 +22,7 @@ properties: > - enum: > - mediatek,mt2712-wdt > - mediatek,mt6589-wdt > + - mediatek,mt6735-wdt > - mediatek,mt6795-wdt > - mediatek,mt7986-wdt > - mediatek,mt8183-wdt > diff --git a/include/dt-bindings/reset/mediatek,mt6735-wdt.h b/include/dt-bindings/reset/mediatek,mt6735-wdt.h > new file mode 100644 > index 000000000000..c6056e676d46 > --- /dev/null > +++ b/include/dt-bindings/reset/mediatek,mt6735-wdt.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_RESET_MEDIATEK_MT6735_WDT_H_ > +#define _DT_BINDINGS_RESET_MEDIATEK_MT6735_WDT_H_ > + > +#define MT6735_TOPRGU_MM_RST 1 > +#define MT6735_TOPRGU_MFG_RST 2 > +#define MT6735_TOPRGU_VENC_RST 3 > +#define MT6735_TOPRGU_VDEC_RST 4 > +#define MT6735_TOPRGU_IMG_RST 5 > +#define MT6735_TOPRGU_MD_RST 7 > +#define MT6735_TOPRGU_CONN_RST 9 > +#define MT6735_TOPRGU_C2K_SW_RST 14 > +#define MT6735_TOPRGU_C2K_RST 15 > +#define MT6735_TOPRGU_RST_NUM 9 > + > +#endif