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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i6-20020a170902c94600b001a666ff198esi11657428pla.545.2023.04.17.02.28.26; Mon, 17 Apr 2023 02:28:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=WV7PTmUG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230317AbjDQJ1X (ORCPT + 99 others); Mon, 17 Apr 2023 05:27:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230304AbjDQJ1I (ORCPT ); Mon, 17 Apr 2023 05:27:08 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98F761BCB; Mon, 17 Apr 2023 02:27:07 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id dm2so62464795ejc.8; Mon, 17 Apr 2023 02:27:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681723627; x=1684315627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9o2pg3w12ouavDje0N4JvwoYzLr+bTenfDLP4dMvvbI=; b=WV7PTmUGJUTWzo0TE4wOxhZM19buPC/10W4ajS3dSrvwsaDIcykO++vhlZUifCFDQV 97XATADfA8pnlPMXfN+NLVPf+PcO2BfHfuUJlfE/nW8Dz4gwW7m86WNU9HhAQ4l8j+Ul 7KEAG9od5Ot3r7ndyR6lGhUN+WGBfNgbOWQ7AHIJYKl85ZkA1/wO7RCmqYELrgFBCU+M kx5CJq9Owr7hg6T532sl0h6sG6L3TvS300kUbKCFGc4lVusk643zGZbOkoiUDYGtSVv1 DMp/2fXt7+NcnYS01/l0vpQ1Lru6WKb9iFrx0RtRPxs6dP27CQ3hkMwoQNGNhKh2rC8/ YcZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681723627; x=1684315627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9o2pg3w12ouavDje0N4JvwoYzLr+bTenfDLP4dMvvbI=; b=JPooHZV1njf7EmvDtALc95YuGXCu2Kei8Jxbp+KCk3uT4C7mE3O163DTsBC6Dc6Fk5 qocpI3x9ScX7wYkxFbfgvnzhlC+qWwOZ5YNt/MEgrbgMZJInWwXso/B2PD7+qpVma3Tk 2P79WTPZCU1SWJIj+DS0C6YRIGNVdSggvCG/0PXNom4Wtxa7k2jxJyP9wTQtnypRld61 70JG7pZ+3fKp7DPbmxY4/m40KWGmWikPNcJUsPfS6Z8hnMq3N6XKoqSh3SxP5+N/VRDx 1PjTV1hGhLgkFRwsuFh29mqOIJuawzTOLOA7KDMxeDENnq8vI8aybeV4bOJNO86KVcd6 /fZA== X-Gm-Message-State: AAQBX9fc6V1B+/iUrsOEC5vNni8JYJHwaR3aLKBLyPYN96D5LngVq/Xr jvACaYHcJomSjKhL9ZnEOiU= X-Received: by 2002:a17:906:4098:b0:94f:cc7:fd7f with SMTP id u24-20020a170906409800b0094f0cc7fd7fmr7143125ejj.65.1681723627086; Mon, 17 Apr 2023 02:27:07 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id p20-20020a170906615400b0094aa087578csm6398596ejl.171.2023.04.17.02.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 02:27:06 -0700 (PDT) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, Rick Wertenbroek , stable@vger.kernel.org, Damien Le Moal , Shawn Lin , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Brian Norris , Caleb Connolly , Corentin Labbe , Johan Jonker , Judy Hsiao , Hugh Cole-Baker , Arnaud Ferraris , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/11] PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked Date: Mon, 17 Apr 2023 11:26:22 +0200 Message-Id: <20230417092631.347976-5-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230417092631.347976-1-rick.wertenbroek@gmail.com> References: <20230417092631.347976-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The RK3399 PCIe controller should wait until the PHY PLLs are locked. Add poll and timeout to wait for PHY PLLs to be locked. If they cannot be locked generate error message and jump to error handler. Accessing registers in the PHY clock domain when PLLs are not locked causes hang The PHY PLLs status is checked through a side channel register. This is documented in the TRM section 17.5.8.1 "PCIe Initialization Sequence". Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek Reviewed-by: Damien Le Moal Tested-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip.c | 17 +++++++++++++++++ drivers/pci/controller/pcie-rockchip.h | 2 ++ 2 files changed, 19 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 990a00e08bc5..1aa84035a8bc 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -153,6 +154,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) } EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); +#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr) +/* 100 ms max wait time for PHY PLLs to lock */ +#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000 +/* Sleep should be less than 20ms */ +#define RK_PHY_PLL_LOCK_SLEEP_US 1000 + int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; @@ -254,6 +261,16 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } + err = readx_poll_timeout(rockchip_pcie_read_addr, + PCIE_CLIENT_SIDE_BAND_STATUS, + regs, !(regs & PCIE_CLIENT_PHY_ST), + RK_PHY_PLL_LOCK_SLEEP_US, + RK_PHY_PLL_LOCK_TIMEOUT_US); + if (err) { + dev_err(dev, "PHY PLLs could not lock, %d\n", err); + goto err_power_off_phy; + } + /* * Please don't reorder the deassert sequence of the following * four reset pins. diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 51a123e5c0cf..f3a5ff1cf7f4 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -38,6 +38,8 @@ #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) +#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) +#define PCIE_CLIENT_PHY_ST BIT(12) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) #define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 -- 2.25.1