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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 186-20020a6307c3000000b0051b54dccfffsi10524074pgh.721.2023.04.17.03.22.42; Mon, 17 Apr 2023 03:22:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=IDSBMgZa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229898AbjDQKKg (ORCPT + 99 others); Mon, 17 Apr 2023 06:10:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230024AbjDQKKc (ORCPT ); Mon, 17 Apr 2023 06:10:32 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23CFC6A6B; Mon, 17 Apr 2023 03:09:53 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EC46260F88; Mon, 17 Apr 2023 10:09:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B352C433EF; Mon, 17 Apr 2023 10:09:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681726192; bh=V2wRmJnf4rtafpsOkImRTxfzgqylAUh6GeAuaVADOEE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=IDSBMgZaUB6h4K/xRHyNbJ0+FPiLxFUaTIA/4JbCSDGEIVMTsb1rri4xCSawZRHq/ tCJt/BlNpLib4A56TOXVa2QPwLvRrJxhS1EN0LoulgLbtc/edlWvFVi8sYh5utVQCb H9KXO+8ZO3IID9Y42yrNDJRLxN5CI08OqU1F8uyOO9ed+UYEv/EcPrGN6ZYramaO+P +9XVbgbMAelOxurNYoUM+DeeAArmZW7/T2r+QxpoCY8f1PqVNLTifM7DWCG7SEuG8c vXIwlFFf7twube4Ie3sMQRyDAQWCkLtIG3zvNnH4nL4weAl9rT4dx6HONe3LofIXSE 7mntqs+tkM7CQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1poLnx-008yiv-VB; Mon, 17 Apr 2023 11:09:50 +0100 Date: Mon, 17 Apr 2023 11:09:49 +0100 Message-ID: <86cz42lt02.wl-maz@kernel.org> From: Marc Zyngier To: AngeloGioacchino Del Regno Cc: walter.chang@mediatek.com, Catalin Marinas , Will Deacon , Jonathan Corbet , Daniel Lezcano , Thomas Gleixner , Mark Rutland , Matthias Brugger , wsd_upstream@mediatek.com, stanley.chu@mediatek.com, Chun-hung.Wu@mediatek.com, Freddy.Hsin@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH] clocksource/drivers/arm_arch_timer: Add workaround for MediaTek MMIO timer In-Reply-To: References: <20230417090635.13202-1-walter.chang@mediatek.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: angelogioacchino.delregno@collabora.com, walter.chang@mediatek.com, catalin.marinas@arm.com, will@kernel.org, corbet@lwn.net, daniel.lezcano@linaro.org, tglx@linutronix.de, mark.rutland@arm.com, matthias.bgg@gmail.com, wsd_upstream@mediatek.com, stanley.chu@mediatek.com, Chun-hung.Wu@mediatek.com, Freddy.Hsin@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 17 Apr 2023 11:01:15 +0100, AngeloGioacchino Del Regno wrote: > > Il 17/04/23 11:06, walter.chang@mediatek.com ha scritto: > > From: Walter Chang > > > > The MT69XX series SoCs have the incomplete implementation issue in the > > mmio timer. Specifically, the hardware only implements the TVAL > > functionality, but not the CVAL functionality. This hardware limitation > > will cause set_next_event_mem() fail to set the actual expiration time > > when writing a value to the CVAL. On these platforms, the mmio timer's > > internal expiration time will still be judged as 0 (the value of TVAL), > > resulting in the mmio timer not functioning as intended. > > > > The workaround is to use TVAL in addition to CVAL for these affected > > platforms. > > > > Signed-off-by: Walter Chang > > --- > > Documentation/arm64/silicon-errata.rst | 4 ++++ > > drivers/clocksource/Kconfig | 9 ++++++++ > > drivers/clocksource/arm_arch_timer.c | 29 ++++++++++++++++++++++++++ > > 3 files changed, 42 insertions(+) > > > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > > index ec5f889d7681..ca1893713a4c 100644 > > --- a/Documentation/arm64/silicon-errata.rst > > +++ b/Documentation/arm64/silicon-errata.rst > > @@ -209,3 +209,7 @@ stable kernels. > > +----------------+-----------------+-----------------+-----------------------------+ > > | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | > > +----------------+-----------------+-----------------+-----------------------------+ > > + > > ++----------------+-----------------+-----------------+-----------------------------+ > > +| MediaTek | MT69XX series | #690001 | MEDIATEK_ERRATUM_690001 | > > ++----------------+-----------------+-----------------+-----------------------------+ > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > > index 5fc8f0e7fb38..475356b8dbdc 100644 > > --- a/drivers/clocksource/Kconfig > > +++ b/drivers/clocksource/Kconfig > > @@ -368,6 +368,15 @@ config SUN50I_ERRATUM_UNKNOWN1 > > the Allwinner A64 SoC. The workaround will only be active if the > > allwinner,erratum-unknown1 property is found in the timer node. > > +config MEDIATEK_ERRATUM_690001 > > + bool "Workaround for MediaTek MT69XX erratum 690001" > > + depends on ARM_ARCH_TIMER && ARM64 > > + help > > + This option enables a workaround for incomplete implementation > > + in the MMIO timer on the MediaTek MT69XX SoCs. The workaround > > + will only be active if mediatek,erratum-690001 property is > > + found in the timer node. > > + > > config ARM_GLOBAL_TIMER > > bool "Support for the ARM global timer" if COMPILE_TEST > > select TIMER_OF if OF > > diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c > > index e09d4427f604..920570d57fc0 100644 > > --- a/drivers/clocksource/arm_arch_timer.c > > +++ b/drivers/clocksource/arm_arch_timer.c > > @@ -389,6 +389,10 @@ static u64 notrace sun50i_a64_read_cntvct_el0(void) > > } > > #endif > > +#ifdef CONFIG_MEDIATEK_ERRATUM_690001 > > +static bool arch_timer_mem_sne_use_tval __ro_after_init; > > What about reusing part of the CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND logic and > adding something like CONFIG_ARM_ARCH_TIMER_MEM_WORKAROUND? I don't think there is *any* need for the out-of-line stuff on any of the memory-mapped accesses, if only because they are not inlined the first place, and that there is no performance requirements around this timer (it should hardly ever be used as the sched clock, for example). Despite being part of the same driver, the sysreg and MMIO timers are vastly different and keeping them together has only been a nuisance. Someone should throw an axe at this stuff. M. -- Without deviation from the norm, progress is not possible.