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 <c1f32d73-a311-6d70-0be6-12bdb50a052f@linaro.org>
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From:   Yangfl <mmyangfl@gmail.com>
Date:   Tue, 18 Apr 2023 01:47:57 +0800
Message-ID: <CAAXyoMPz1ONgDvFET0dFKBktODoSY2m3ubHfmVBsJ46sRBF31w@mail.gmail.com>
Subject: Re: [PATCH 1/2] dt-bindings: clock: Add reg-clock-controller
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc:     linux-clk@vger.kernel.org,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
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Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> =E4=BA=8E2023=E5=B9=B4=
4=E6=9C=8815=E6=97=A5=E5=91=A8=E5=85=AD 05:08=E5=86=99=E9=81=93=EF=BC=9A
>
> On 14/04/2023 20:12, David Yang wrote:
> > Add DT bindings documentation for reg-clock-controller, collection of
> > basic clocks common to many platforms.
> >
> > Signed-off-by: David Yang <mmyangfl@gmail.com>
> > ---
> >  .../bindings/clock/reg-clock-controller.yaml  | 245 ++++++++++++++++++
> >  1 file changed, 245 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/reg-clock-c=
ontroller.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/reg-clock-controll=
er.yaml b/Documentation/devicetree/bindings/clock/reg-clock-controller.yaml
> > new file mode 100644
> > index 000000000000..a6a7e0b05821
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/reg-clock-controller.yaml
> > @@ -0,0 +1,245 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/reg-clock-controller.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Simple straight-forward register-based clocks
> > +
> > +maintainers:
> > +  - David Yang <mmyangfl@gmail.com>
> > +
> > +description: |
> > +  Basic clocks common to many platforms.
> > +
> > +  If your clocks don't fit into these catagories, simply create your c=
lock
>
> typo: categories

Fixed in v2.

>
> > +  controller. This driver normally work well with other controllers as=
 long as
> > +  they operate on different registers.
> > +
> > +  See linux/clk-provider.h for details about properties for each type =
of clock.
>
> Describe here what is this device, what such simple clock controller
> represents.

Description has been rewritten in v3, to describe the device.

>
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - reg-clock-controller
> > +
> > +  ranges: true
> > +
> > +  '#address-cells':
> > +    const: 1
> > +
> > +  '#size-cells':
> > +    const: 1
> > +
> > +required:
> > +  - compatible
> > +  - ranges
> > +  - '#address-cells'
> > +  - '#size-cells'
>
> required goes after patternProperties.

Fixed in v2.

>
> > +
> > +patternProperties:
> > +  ".*gate-clock@.*":
>
> "gate-clock@" should be equivalent. However this should be just "clock".

Fixed in v3.

>
> > +    type: object
> > +
> > +    description: |
>
> Do not need '|' unless you need to preserve formatting.

Fixed in v2.

>
> > +      Clock which can gate its output.
> > +
> > +    properties:
> > +      compatible:
> > +        const: gate-clock
> > +
> > +      reg:
> > +        maxItems: 1
> > +
> > +      '#clock-cells':
> > +        const: 0
> > +
> > +      clocks:
> > +        maxItems: 1
> > +        description:
> > +          Parent clock.
> > +
> > +      clock-output-name:
>
> names
>
> Don't create your own properties.

Fixed in v2, "clock-output-names".

>
> > +        maxItems: 1
> > +
> > +      bit-index:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Bit index which controls the output.
>
> I suggest to use same property as nvme, so bits.

Replaced with "bits" in v2.

>
> > +
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - '#clock-cells'
> > +      - bit-index
> > +
> > +    additionalProperties: false
> > +
> > +  ".*divider-clock@.*":
> > +    type: object
> > +
> > +    description: |
> > +      Clock with an adjustable divider affecting its output frequency.
> > +
> > +    properties:
> > +      compatible:
> > +        const: divider-clock
> > +
> > +      reg:
> > +        maxItems: 1
> > +
> > +      '#clock-cells':
> > +        const: 0
> > +
> > +      clocks:
> > +        description:
> > +          Parent clocks.
> > +
> > +      clock-output-name:
> > +        maxItems: 1
> > +
> > +      shift:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Shift to the divider bit field.
> > +
> > +      width:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Width of the divider bit field.
> > +
> > +      dividers:
> > +        $ref: /schemas/types.yaml#/definitions/uint32-array
> > +        description:
> > +          Array of value/divider pairs.
>
> Then it looks like matrix.

This part of bindings has been (temporarily) removed from this series
since v2, to make it simpler.

>
> > +
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - '#clock-cells'
> > +      - shift
> > +      - width
> > +
> > +    additionalProperties: false
> > +
> > +  ".*mux-clock@.*":
> > +    type: object
> > +
> > +    description: |
> > +      Clock with multiple selectable parents.
> > +
> > +    properties:
> > +      compatible:
> > +        const: mux-clock
> > +
> > +      reg:
> > +        maxItems: 1
> > +
> > +      '#clock-cells':
> > +        const: 0
> > +
> > +      clocks:
> > +        minItems: 1
> > +        description:
> > +          Parent clock.
> > +
> > +      clock-output-name:
> > +        maxItems: 1
> > +
> > +      shift:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Shift to multiplexer bit field.
> > +
> > +      mask:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Mask of mutliplexer bit field.
> > +
> > +      table:
> > +        $ref: /schemas/types.yaml#/definitions/uint32-array
> > +        description:
> > +          Array of register values corresponding to the parent index.
> > +
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - '#clock-cells'
> > +      - shift
> > +      - mask
> > +
> > +    additionalProperties: false
> > +
> > +  ".*fractional-divider-clock@.*":
> > +    type: object
> > +
> > +    description: |
> > +      Clock with adjustable fractional divider affecting its output fr=
equency.
> > +
> > +    properties:
> > +      compatible:
> > +        const: fractional_divider-clock
> > +
> > +      reg:
> > +        maxItems: 1
> > +
> > +      '#clock-cells':
> > +        const: 0
> > +
> > +      clocks:
> > +        maxItems: 1
> > +        description:
> > +          Parent clock.
> > +
> > +      clock-output-name:
> > +        maxItems: 1
> > +
> > +      numerator-shift:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Shift to the numerator bit field.
> > +
> > +      numerator-width:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Width of the numerator bit field.
> > +
> > +      denominator-shift:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Shift to the denominator bit field.
> > +
> > +      denominator-width:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Width of the denominator bit field.
> > +
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - '#clock-cells'
> > +      - numerator-shift
> > +      - numerator-width
> > +      - denominator-shift
> > +      - denominator-width
> > +
> > +    additionalProperties: false
> > +
> > +additionalProperties: true
>
> No, come on. This must be false.

Fixed with "false" in v2.

>
> > +
> > +examples:
> > +  - |
> > +    clks: reg-clk-ctrl@ffff0000 {
>
> Names should be generic, so clock-controller
>
> Drop the label.

Dropped in v2.

>
> > +      compatible =3D "reg-clock-controller";
> > +      #address-cells =3D <1>;
> > +      #size-cells =3D <1>;
> > +      ranges =3D <0 0xffff0000 0x1000>;
> > +
> > +      my_clk: gate-clock@cc-3 {
>
> Drop label.
>
> That's a new unit address to me. Did I miss a change in DT spec?

Dropped label in v2.

>
> > +        compatible =3D "gate-clock";
> > +        #clock-cells =3D <0>;
> > +        reg =3D <0xcc 4>;
>
> reg is after compatible.
>
> > +        bit-index =3D <3>;
> > +        clock-output-name =3D "my-clk";
>
> Plus, test your patches. This fails testing...

Fix name error in v3.

>
> > +      };
> > +    };
>
> Best regards,
> Krzysztof
>