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Tue, 18 Apr 2023 03:21:57 -0700 Received: from [10.41.21.79] (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 18 Apr 2023 03:21:52 -0700 Message-ID: <71e45a06-6b02-6b29-b9d9-0c34ff508b64@nvidia.com> Date: Tue, 18 Apr 2023 15:51:49 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [Patch v6 6/9] cpufreq: tegra194: add OPP support and set bandwidth Content-Language: en-US To: Viresh Kumar CC: , , , , , , , , , , , , , , , , , , , , , Sumit Gupta References: <20230411110002.19824-1-sumitg@nvidia.com> <20230411110002.19824-7-sumitg@nvidia.com> <20230418091315.bxh4hp6g3vekdi2r@vireshk-i7> From: Sumit Gupta In-Reply-To: <20230418091315.bxh4hp6g3vekdi2r@vireshk-i7> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT043:EE_|DM6PR12MB4942:EE_ X-MS-Office365-Filtering-Correlation-Id: 844a4177-1932-41bf-12ea-08db3ff6c5bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 10:22:11.2811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 844a4177-1932-41bf-12ea-08db3ff6c5bc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4942 X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/04/23 14:43, Viresh Kumar wrote: > External email: Use caution opening links or attachments > > > On 11-04-23, 16:29, Sumit Gupta wrote: >> Add support to use OPP table from DT in Tegra194 cpufreq driver. >> Tegra SoC's receive the frequency lookup table (LUT) from BPMP-FW. >> Cross check the OPP's present in DT against the LUT from BPMP-FW >> and enable only those DT OPP's which are present in LUT also. >> >> The OPP table in DT has CPU Frequency to bandwidth mapping where >> the bandwidth value is per MC channel. DRAM bandwidth depends on the >> number of MC channels which can vary as per the boot configuration. >> This per channel bandwidth from OPP table will be later converted by >> MC driver to final bandwidth value by multiplying with number of >> channels before sending the request to BPMP-FW. >> >> If OPP table is not present in DT, then use the LUT from BPMP-FW >> directy as the CPU frequency table and not do the DRAM frequency >> scaling which is same as the current behavior. >> >> Now, as the CPU Frequency table is being controlling through OPP >> table in DT. Keeping fewer entries in the table will create less >> frequency steps and can help to scale fast to high frequencies >> when required. >> >> Signed-off-by: Sumit Gupta >> --- >> drivers/cpufreq/tegra194-cpufreq.c | 156 ++++++++++++++++++++++++++--- >> 1 file changed, 143 insertions(+), 13 deletions(-) > > Can this be applied independently of the rest of the series ? > > -- > viresh Yes, this can be applied independently. Thank you, Sumit Gupta