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Date:   Tue, 18 Apr 2023 18:28:00 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Mason Huo <mason.huo@starfivetech.com>
Cc:     "Rafael J. Wysocki" <rafael@kernel.org>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Shengyu Qu <wiagn233@outlook.com>, linux-pm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110
 SoC
Message-ID: <20230418-talcum-unthread-618a5bd2758a@spud>
References: <20230417063942.3141-1-mason.huo@starfivetech.com>
 <20230417063942.3141-4-mason.huo@starfivetech.com>
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Hey Mason,

Just one minor comment in passing..

On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote:
> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
> It supports up to 4 cpu frequency loads.
>=20
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
>  .../jh7110-starfive-visionfive-2.dtsi         | 17 ++++++++++
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 33 +++++++++++++++++++
>  2 files changed, 50 insertions(+)
>=20
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dt=
si b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index cca1c8040801..b25e6d68ce53 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -227,3 +227,20 @@ &uart0 {
>  	pinctrl-0 =3D <&uart0_pins>;
>  	status =3D "okay";
>  };
> +
> +&U74_1 {
> +	cpu-supply =3D <&vdd_cpu>;
> +};
> +
> +&U74_2 {
> +	cpu-supply =3D <&vdd_cpu>;
> +};
> +
> +&U74_3 {
> +	cpu-supply =3D <&vdd_cpu>;
> +};
> +
> +&U74_4 {
> +	cpu-supply =3D <&vdd_cpu>;
> +};
> +

Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC
/stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF.
+
warning: 1 line adds whitespace errors.

Cheers,
Conor.


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