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From:   Joy Chakraborty <joychakr@google.com>
Date:   Wed, 19 Apr 2023 11:18:25 +0530
Message-ID: <CAOSNQF2sXHFCx9ZfrtfmxHfKrAE0XGP8SRvW6wyYco+FKSPmDw@mail.gmail.com>
Subject: Re: [PATCH v7 4/5] spi: dw: Add DMA address widths capability check
To:     Andy Shevchenko <andriy.shevchenko@intel.com>
Cc:     Serge Semin <fancer.lancer@gmail.com>,
        Mark Brown <broonie@kernel.org>, linux-spi@vger.kernel.org,
        linux-kernel@vger.kernel.org, manugautam@google.com,
        rohitner@google.com
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On Tue, Apr 18, 2023 at 1:08=E2=80=AFPM Andy Shevchenko
<andriy.shevchenko@intel.com> wrote:
>
> On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:
> > Store address width capabilities of DMA controller during init and chec=
k
> > the same per transfer to make sure the bits/word requirement can be met=
.
> >
> > Current DW DMA driver requires both tx and rx channel to be configured
> > and functional hence a subset of both tx and rx channel address width
> > capability is checked with the width requirement(n_bytes) for a
> > transfer.
>
> ...
>
> > +     /*
> > +      * Assuming both channels belong to the same DMA controller hence=
 the
> > +      * address width capabilities most likely would be the same.
> > +      */
>
> I had a small comment on this In v6 thread.

Sure,

Your comment in V6 thread:
"
I would add something to explain the side of these address width, like

         * Assuming both channels belong to the same DMA controller hence
         * the peripheral side address width capabilities most likely would
         * be the same.
"

I do not think the address width capabilities are dependent on the
side of generation like memory or peripheral. From what I understand,
address width capabilities are solely dependent on the transaction
generation capability of the DMA controller towards the system bus.
What we intend to highlight here is the assumption that both tx and rx
channel would belong to the same DMA controller hence the transaction
generation capabilities would be the same both for read and write
(e.g. if the DMA controller is able to generate 32 bit sized reads
then it should also be able to generate 32 bit sized writes).
With this assumption we are doing a bitwise and of both tx and rx capabilit=
ies.

Please let me know if you think otherwise.

Thanks
Joy

>
> --
> With Best Regards,
> Andy Shevchenko
>
>