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Wed, 19 Apr 2023 16:08:41 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33JG8e5e019112 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Apr 2023 16:08:40 GMT Received: from [10.110.10.142] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 19 Apr 2023 09:08:39 -0700 Message-ID: <9808142e-d6e6-71bc-f362-09b878cb3b87@quicinc.com> Date: Wed, 19 Apr 2023 09:08:38 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH V22 2/3] misc: dcc: Add driver support for Data Capture and Compare unit(DCC) Content-Language: en-US To: Souradeep Chowdhury , Arnd Bergmann , Greg Kroah-Hartman CC: Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Bjorn Andersson , Rob Herring , Alex Elder , , , , , Sibi Sankar , Rajendra Nayak References: <2023041833-alienate-trash-f4da@gregkh> <50844899-b047-42fd-807a-db7136e5e590@app.fastmail.com> <44834c75-4db7-ec8a-9367-c6b83fa96b22@quicinc.com> From: Trilok Soni In-Reply-To: <44834c75-4db7-ec8a-9367-c6b83fa96b22@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MwTmVPbXfvqJz-nmmImwrS4c6f1USKpV X-Proofpoint-ORIG-GUID: MwTmVPbXfvqJz-nmmImwrS4c6f1USKpV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-19_10,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 clxscore=1011 mlxscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304190145 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/19/2023 3:20 AM, Souradeep Chowdhury wrote: > > > On 4/19/2023 1:00 PM, Arnd Bergmann wrote: >> On Wed, Apr 19, 2023, at 09:00, Souradeep Chowdhury wrote: >>> On 4/18/2023 9:15 PM, Greg Kroah-Hartman wrote: >>>> >>>>> The following is the justification of using debugfs interface over the >>>>> other alternatives like sysfs/ioctls >>>>> >>>>> i) As can be seen from the debugfs attribute descriptions, some of the >>>>> debugfs attribute files here contains multiple arguments which >>>>> needs to >>>>> be accepted from the user. This goes against the design style of >>>>> sysfs. >>>>> >>>>> ii) The user input patterns have been made simple and convenient in >>>>> this >>>>> case with the use of debugfs interface as user doesn't need to shuffle >>>>> between different files to execute one instruction as was the case on >>>>> using other alternatives. >>>> >>>> Why do you have debugfs and also a misc device?  How are they related? >>>> Why both?  Why not just one?  What userspace tools are going to use >>>> either of these interfaces and where are they published to show how >>>> this >>>> all was tested? >>> >>> DCC has two fundamental steps of usage:- >>> >>> 1.Configuring the register addresses on the dcc_sram which is done by >>> user through the debugfs interface. For example:- >>> >>> echo R 0x10c004 > /sys/kernel/debug/dcc/../3/config >>> >>> Here we are configuring the register addresses for list 3, the 'R' >>> indicates a read operation, so this register value will be read >>> in case of a software trigger or kernel panic/watchdog bite and >>> dumped into the dcc_sram. >> >> Can you describe why the register location needs to be >> runtime configurable? I would have expected this type of setting >> to be part of the devicetree, which already describes other >> parts that interact with sram devices. > > Register addresses are made runtime configurable to give the user the > option of going for a software trigger. So the user can debug issues > during run-time as well. These register locations are arbitrary > and is configured by the user for debugging purposes and is not related > to the DCC hardware itself. Please note that we don't want to recompile the devicetree for new settings since these registers can be set by team of engineers who are debugging system level issues with various IPs across the SOCs. You don't want to recompile the images while reproducing the system hangs/IP watchdogs etc; ---Trilok Soni