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Date:   Wed, 19 Apr 2023 20:35:07 +0300
From:   Andy Shevchenko <andriy.shevchenko@intel.com>
To:     Joy Chakraborty <joychakr@google.com>
Cc:     Serge Semin <fancer.lancer@gmail.com>,
        Mark Brown <broonie@kernel.org>, linux-spi@vger.kernel.org,
        linux-kernel@vger.kernel.org, manugautam@google.com,
        rohitner@google.com
Subject: Re: [PATCH v7 4/5] spi: dw: Add DMA address widths capability check
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On Wed, Apr 19, 2023 at 06:18:04PM +0530, Joy Chakraborty wrote:
> On Wed, Apr 19, 2023 at 5:19 PM Andy Shevchenko
> <andriy.shevchenko@intel.com> wrote:
> > On Wed, Apr 19, 2023 at 11:18:25AM +0530, Joy Chakraborty wrote:
> > > On Tue, Apr 18, 2023 at 1:08 PM Andy Shevchenko
> > > <andriy.shevchenko@intel.com> wrote:
> > > > On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:

...

> > > > > +     /*
> > > > > +      * Assuming both channels belong to the same DMA controller hence the
> > > > > +      * address width capabilities most likely would be the same.
> > > > > +      */
> > > >
> > > > I had a small comment on this In v6 thread.
> > >
> > > Sure,
> > >
> > > Your comment in V6 thread:
> > > "
> > > I would add something to explain the side of these address width, like
> > >
> > >          * Assuming both channels belong to the same DMA controller hence
> > >          * the peripheral side address width capabilities most likely would
> > >          * be the same.
> > > "
> > >
> > > I do not think the address width capabilities are dependent on the
> > > side of generation like memory or peripheral.
> >
> > Yes, they are independent. Memory could do with 4 bytes, while peripheral with
> > 1 byte and so on.
> >
> > > From what I understand,
> > > address width capabilities are solely dependent on the transaction
> > > generation capability of the DMA controller towards the system bus.
> >
> > What do you mean by a SB in the above? Memory? Peripheral?
> 
> By system bus I mean anything that is connecting the Memory, DMA and
> the peripheral.
> Something like :
> 
>           +-----------+          +-------------------+
>           |               |           |                        |
>           |   DMA    |           | PERIPHERAL |
>           |               |           |                         |
>           +----^-+---+          +-----+--^---------+
>         *** -->| |                         |    |
>                   | |                         |    |
> <------------+-v--------------------v---+------------->
>                     SYSTEM BUS
> <---------------------+--^----------------------------->
>                             |   |
>                             |   |
>                      +----v--+-----+
>                      |                   |
>                      |  MEMORY |
>                      |                   |
>                      +--------------+
> *** : Address width capabilities should be the capability of the DMA
> to generate transactions to the system bus on the marked interface
> irrespective of whether it is destined for Peripheral or memory is
> what I understand.

That's misunderstanding. You used only one possible HW design, there may be
more. For example we have Synopsys DesignWare DMA that has a lot of parameters
to configure bus mastering. One of such a case, where it makes a lot of sense,
is DesignWare SATA with the above mentioned DMA controller where it has two
masters and they are connected towards memory and towards peripheral "buses".
They have _different_ configurations.

So, generally speaking what you are saying is not true.

> > > What we intend to highlight here is the assumption that both tx and rx
> > > channel would belong to the same DMA controller hence the transaction
> > > generation capabilities would be the same both for read and write
> > > (e.g. if the DMA controller is able to generate 32 bit sized reads
> > > then it should also be able to generate 32 bit sized writes).
> > > With this assumption we are doing a bitwise and of both tx and rx capabilities.
> > >
> > > Please let me know if you think otherwise.

-- 
With Best Regards,
Andy Shevchenko