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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id k25-20020a2e2419000000b002a8dce82cf6sm28853ljk.32.2023.04.19.18.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 18:14:56 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH 0/2] DPU1 GC1.8 wiring-up Date: Thu, 20 Apr 2023 03:14:53 +0200 Message-Id: <20230420-topic-dpu_gc-v1-0-d9d1a5e40917@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAA2SQGQC/x2NWwqDMBAAryL77UKMr9arSCl5rLogMSRVCuLdX fycgWFOyJSYMgzFCYkOzrwFgaoswC0mzITshUErXatGK/xtkR36uH9nh91bVVPf9t3LW5DEmkx okwlukSjs6yoyJpr4/zzGz3XdvYT8T3MAAAA= To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681953295; l=1362; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=pRHWMRjt/n9zLCczjy/Yn/VbOiBgkQ1FtQZWTc9Q9rU=; b=JJ6i5qpF1MvRqD4DAygLVZUDtlpMNWpPh9eMvOEZe+8x04Wtsqq7pdDXh7F7vxVR2O7WsS1fScsC xwAzpJkqCZ/+gAiDEimRKnfQG7CuG6aVE522+WRSzEaNoA4nw444 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Almost all SoCs from SDM845 to SM8550 inclusive feature a GC1.8 dspp sub-block in addition to PCCv4. The other block differ a bit more, but none of them are supported upstream. This series adds configures the GCv1.8 on all the relevant SoCs. Signed-off-by: Konrad Dybcio --- Konrad Dybcio (2): drm/msm/dpu1: Rename sm8150_dspp_blk to sdm845_dspp_blk drm/msm/dpu1: Enable GCv1.8 on many SoCs drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 16 ++++++++-------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 16 ++++++++-------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 16 ++++++++-------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 16 ++++++++-------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 16 ++++++++-------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16 ++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +++- 9 files changed, 55 insertions(+), 53 deletions(-) --- base-commit: 3cdbc01c40e34c57697f8934f2727a88551696be change-id: 20230420-topic-dpu_gc-6901f75768db Best regards, -- Konrad Dybcio