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bh=cOz2vJX6O8WYQA+86dOvET6FW/q2m4As7J1doBwYieQ=; b=K7GJ+/ZbxVdD6BYEsEznRoGDvP4YwN94wcFwIA1FWRjnm0PBTD4hpwXZuZazCW8gsC g/ymRW9AWfpaSD6J1sbUqD0JZ7vKYRZTv09krRxR5TxUHmunaFYOJ+zAB8wbDWmtV2j9 +xNWi9uROBaep8F10Imnlf93MoOK8YnAjNArs3xgt4gBuh204u+hfNqldjxOVPgI+eeV 7he0LF4ssXLrOIwKBpKuehgWdXvP2plAv+72f6lGzlMQTwtIZ+10TpBuGfXL1ONufoU9 77oK/+bOnxLyRQX+snvuwHtzBTmhOdpXFYE7lxzsf0nhx+CTifS2HenlmbJD8R0X6VZY H41Q== X-Gm-Message-State: AAQBX9cmc7MimmaYOQbcPuJWxHpFNUNMAgDjIh6hbFauNUQPeG+f9imQ MfMTRvcYFQrXchJTHZjxHcJFeJuotseAfibim2s= X-Received: by 2002:a0d:e0c1:0:b0:54c:1405:2ce with SMTP id j184-20020a0de0c1000000b0054c140502cemr712660ywe.49.1681995657810; Thu, 20 Apr 2023 06:00:57 -0700 (PDT) MIME-Version: 1.0 References: <3b9c4f05eaf14bc3b16aebec3ff84c8a2d52c4a5.1681887790.git.zhoubinbin@loongson.cn> In-Reply-To: From: Binbin Zhou Date: Thu, 20 Apr 2023 21:00:42 +0800 Message-ID: Subject: Re: [PATCH V3 1/2] dt-bindings: interrupt-controller: Add Loongson EIOINTC To: Krzysztof Kozlowski Cc: Binbin Zhou , Huacai Chen , WANG Xuerui , Jiaxun Yang , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Jianmin Lv , Huacai Chen , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, loongarch@lists.linux.dev, devicetree@vger.kernel.org, loongson-kernel@lists.loongnix.cn Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 20, 2023 at 4:09=E2=80=AFAM Krzysztof Kozlowski wrote: > > On 19/04/2023 09:17, Binbin Zhou wrote: > > Add Loongson Extended I/O Interrupt controller binding with DT schema > > format using json-schema. > > > > Signed-off-by: Binbin Zhou > > --- > > .../loongson,eiointc.yaml | 74 +++++++++++++++++++ > > 1 file changed, 74 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-control= ler/loongson,eiointc.yaml > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/loo= ngson,eiointc.yaml b/Documentation/devicetree/bindings/interrupt-controller= /loongson,eiointc.yaml > > new file mode 100644 > > index 000000000000..4ab4efb061e1 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,e= iointc.yaml > > @@ -0,0 +1,74 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/interrupt-controller/loongson,eioin= tc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Loongson Extended I/O Interrupt Controller > > + > > +maintainers: > > + - Binbin Zhou > > + > > +description: | > > + This interrupt controller is found on the Loongson-3 family chips an= d > > + Loongson-2K series chips and is used to distribute interrupts direct= ly to > > + individual cores without forwarding them through the HT's interrupt = line. > > + > > +allOf: > > + - $ref: /schemas/interrupt-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - loongson,ls2k0500-eiointc > > + - loongson,ls2k2000-eiointc > > + > > + reg: > > + items: > > + - description: Interrupt enable registers > > + - description: Interrupt status registers > > + - description: Interrupt clear registers > > + - description: Interrupt routing configuration registers > > + > > + reg-names: > > + items: > > + - const: enable > > + - const: status > > + - const: clear > > + - const: route > > + > > + interrupts: > > + maxItems: 1 > > + > > + interrupt-controller: true > > + > > + '#interrupt-cells': > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-controller > > + - '#interrupt-cells' > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + eiointc: interrupt-controller@1fe11600 { > > + compatible =3D "loongson,ls2k0500-eiointc"; > > + reg =3D <0x1fe11600 0x10>, > > + <0x1fe11700 0x10>, > > + <0x1fe11800 0x10>, > > + <0x1fe114c0 0x4>; > > Binding is OK, but are you sure you want to split the address space like > this? It looks like two address spaces (enable+clear+status should be > one). Are you sure this is correct? > Hi Krzysztof: These registers are all in the range of chip configuration registers, in the case of LS2K0500, which has a base address of 0x1fe10000. However, the individual register addresses are not contiguous with each other, and most are distributed across modules, so I feel that they should be listed in detail as they are used. Thanks. Binbin > Best regards, > Krzysztof > >