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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z13-20020a63c04d000000b00518b499da4csi2441057pgi.71.2023.04.20.15.05.25; Thu, 20 Apr 2023 15:05:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232841AbjDTVzc (ORCPT + 99 others); Thu, 20 Apr 2023 17:55:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232829AbjDTVza (ORCPT ); Thu, 20 Apr 2023 17:55:30 -0400 Received: from relay04.th.seeweb.it (relay04.th.seeweb.it [IPv6:2001:4b7a:2000:18::165]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BEA565AE for ; Thu, 20 Apr 2023 14:55:07 -0700 (PDT) Received: from SoMainline.org (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id D3CCC2049B; Thu, 20 Apr 2023 23:55:04 +0200 (CEST) Date: Thu, 20 Apr 2023 23:55:03 +0200 From: Marijn Suijten To: Dmitry Baryshkov Cc: Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Adam Skladowski , Loic Poulain , Bjorn Andersson , Kuogee Hsieh , Robert Foss , Vinod Koul , Rajesh Yadav , Jeykumar Sankaran , Neil Armstrong , Chandan Uddaraju , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , Archit Taneja , Sravanthi Kollukuduru Subject: Re: [PATCH v2 14/17] drm/msm/dpu: Document and enable TEAR interrupts on DSI interfaces Message-ID: References: <20230411-dpu-intf-te-v2-0-ef76c877eb97@somainline.org> <20230411-dpu-intf-te-v2-14-ef76c877eb97@somainline.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023-04-20 04:11:29, Dmitry Baryshkov wrote: > On 17/04/2023 23:21, Marijn Suijten wrote: > > All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of > > the PINGPONG block and into the INTF block. Wire up these interrupts > > and IRQ masks on all supported hardware. > > > > Signed-off-by: Marijn Suijten > > --- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 ++++++---- > > .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 ++++--- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 ++++--- > > .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 ++++--- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++-- > > .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++---- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 ++++++++++++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 6 +++-- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 27 ++++++++++++++++++++++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 4 ++++ > > 15 files changed, 125 insertions(+), 41 deletions(-) > > If there is v3 for some reason, please split this into two patches: > core/interrups and SoC catalog changes. I think you want a v3 for the vsync_sel _active_ rename in dpu_hw_top, all other patches are r-b'd if I scanned through it all correctly. I can definitely accommodate to that. - Marijn