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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p67-20020a625b46000000b0063d334beed6si3620392pfb.341.2023.04.20.23.29.03; Thu, 20 Apr 2023 23:29:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229624AbjDUGTY (ORCPT + 99 others); Fri, 21 Apr 2023 02:19:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229670AbjDUGSx (ORCPT ); Fri, 21 Apr 2023 02:18:53 -0400 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE67A2729; Thu, 20 Apr 2023 23:18:42 -0700 (PDT) Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.77 with qID 33L6IPuxC024547, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36505.realtek.com.tw[172.21.6.25]) by rtits2.realtek.com.tw (8.15.2/2.81/5.90) with ESMTPS id 33L6IPuxC024547 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Fri, 21 Apr 2023 14:18:26 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.32; Fri, 21 Apr 2023 14:18:26 +0800 Received: from RTEXH36506.realtek.com.tw (172.21.6.27) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Fri, 21 Apr 2023 14:18:25 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server id 15.1.2507.17 via Frontend Transport; Fri, 21 Apr 2023 14:18:25 +0800 From: Stanley Chang To: Thinh Nguyen CC: Stanley Chang , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Felipe Balbi , , , Subject: [PATCH v3 1/2] usb: dwc3: core: add support for remapping global register start address Date: Fri, 21 Apr 2023 14:18:23 +0800 Message-ID: <20230421061825.2233-1-stanley_chang@realtek.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-ServerInfo: RTEXH36505.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The RTK DHC SoCs were designed the global register address offset at 0x8100. The default address offset is constant at DWC3_GLOBALS_REGS_START (0xc100). Therefore, add the property of device-tree to adjust this address offset. Signed-off-by: Stanley Chang --- v2 to v3 change: 1. Fix the dtschema validation error. v1 to v2 change: 1. Change the name of the property "snps,global-regs-starting-offset". 2. Adjust the format of comment. 3. Add initial value of the global_regs_starting_offset 4. Remove the log of dev_info. --- drivers/usb/dwc3/core.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 476b63618511..8c1d1afbdc65 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1785,6 +1785,21 @@ static int dwc3_probe(struct platform_device *pdev) dwc_res = *res; dwc_res.start += DWC3_GLOBALS_REGS_START; + /* + * For some dwc3 controller, the dwc3 global register start address is + * not at DWC3_GLOBALS_REGS_START (0xc100). + */ + if (dev->of_node) { + int global_regs_starting_offset = 0; + + device_property_read_u32(dev, "snps,global-regs-starting-offset", + &global_regs_starting_offset); + if (global_regs_starting_offset) { + dwc_res.start -= DWC3_GLOBALS_REGS_START; + dwc_res.start += global_regs_starting_offset; + } + } + regs = devm_ioremap_resource(dev, &dwc_res); if (IS_ERR(regs)) return PTR_ERR(regs); -- 2.34.1