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From:   Lorenzo Pieralisi <lpieralisi@kernel.org>
To:     tjoseph@cadence.com, robh@kernel.org, kw@linux.com,
        bhelgaas@google.com, nadeem@cadence.com,
        Siddharth Vadapalli <s-vadapalli@ti.com>
Cc:     Lorenzo Pieralisi <lpieralisi@kernel.org>,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, vigneshr@ti.com, srk@ti.com,
        nm@ti.com
Subject: Re: [PATCH v2] PCI: cadence: Fix Gen2 Link Retraining process
Date:   Fri, 21 Apr 2023 11:09:22 +0200
Message-Id: <168206814625.77926.12605918077768300523.b4-ty@kernel.org>
In-Reply-To: <20230315070800.1615527-1-s-vadapalli@ti.com>
References: <20230315070800.1615527-1-s-vadapalli@ti.com>
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On Wed, 15 Mar 2023 12:38:00 +0530, Siddharth Vadapalli wrote:
> The Link Retraining process is initiated to account for the Gen2 defect in
> the Cadence PCIe controller in J721E SoC. The errata corresponding to this
> is i2085, documented at:
> https://www.ti.com/lit/er/sprz455c/sprz455c.pdf
> 
> The existing workaround implemented for the errata waits for the Data Link
> initialization to complete and assumes that the link retraining process
> at the Physical Layer has completed. However, it is possible that the
> Physical Layer training might be ongoing as indicated by the
> PCI_EXP_LNKSTA_LT bit in the PCI_EXP_LNKSTA register.
> 
> [...]

Applied to controller/cadence, thanks!

[1/1] PCI: cadence: Fix Gen2 Link Retraining process
      https://git.kernel.org/pci/pci/c/eac223e85208

Thanks,
Lorenzo