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Wysocki" , Anna-Maria Behnsen , LKML Subject: Re: Loongson (and other $ARCHs?) idle VS timer enqueue Message-ID: <20230422080814.GA1214746@hirez.programming.kicks-ass.net> References: <20230421142446.GA1185829@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 21, 2023 at 06:47:29PM +0200, Frederic Weisbecker wrote: > > *HOWEVER* > > > > intel_idle_irq() is affected -- except that we only (normally) use that > > for very shallow idle states and it won't interact with NOHZ (because we > > only disable the tick for deep idle states). > > Well I don't know, that doesn't look comfortable... :) > > Also why does it need to enable IRQs if ecx=1 ? Supposedly this is some interrupt latency hack. See commit: c227233ad64c ("intel_idle: enable interrupts before C1 on Xeons")