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[209.85.214.177]) by smtp.gmail.com with ESMTPSA id oa16-20020a17090b1bd000b0024721450664sm8486700pjb.41.2023.04.24.10.53.52 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Apr 2023 10:53:53 -0700 (PDT) Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1a6e5be6224so704885ad.1 for ; Mon, 24 Apr 2023 10:53:52 -0700 (PDT) X-Received: by 2002:a05:6e02:1bcd:b0:315:8e3a:f546 with SMTP id x13-20020a056e021bcd00b003158e3af546mr23458ilv.6.1682358812275; Mon, 24 Apr 2023 10:53:32 -0700 (PDT) MIME-Version: 1.0 References: <20230419225604.21204-1-dianders@chromium.org> <20230419155341.v8.3.I6d7f7d5fa0aa293c8c3374194947254b93114d37@changeid> In-Reply-To: <20230419155341.v8.3.I6d7f7d5fa0aa293c8c3374194947254b93114d37@changeid> From: Doug Anderson Date: Mon, 24 Apr 2023 10:53:20 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v8 03/10] arm64: smp: Assign and setup an IPI as NMI To: Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier , Mark Rutland Cc: ito-yuichi@fujitsu.com, kgdb-bugreport@lists.sourceforge.net, Chen-Yu Tsai , Masayoshi Mizuma , Peter Zijlstra , Ard Biesheuvel , "Rafael J . Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Ben Dooks , Pierre Gondois , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, Apr 19, 2023 at 3:57=E2=80=AFPM Douglas Anderson wrote: > > From: Sumit Garg > > Assign an unused IPI which can be turned as NMI using ipi_nmi framework. > Also, invoke corresponding dynamic IPI setup/teardown APIs. > > Signed-off-by: Sumit Garg > Reviewed-by: Masayoshi Mizuma > Tested-by: Chen-Yu Tsai > Signed-off-by: Douglas Anderson > --- > > Changes in v8: > - dynamic_ipi_setup() and dynamic_ipi_teardown() no longer take cpu param > > arch/arm64/kernel/smp.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c > index 4e8327264255..94ff063527c6 100644 > --- a/arch/arm64/kernel/smp.c > +++ b/arch/arm64/kernel/smp.c > @@ -43,6 +43,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -938,6 +939,8 @@ static void ipi_setup(int cpu) > > for (i =3D 0; i < nr_ipi; i++) > enable_percpu_irq(ipi_irq_base + i, 0); > + > + dynamic_ipi_setup(); > } > > #ifdef CONFIG_HOTPLUG_CPU > @@ -950,6 +953,8 @@ static void ipi_teardown(int cpu) > > for (i =3D 0; i < nr_ipi; i++) > disable_percpu_irq(ipi_irq_base + i); > + > + dynamic_ipi_teardown(); > } > #endif > > @@ -971,6 +976,9 @@ void __init set_smp_ipi_range(int ipi_base, int n) > irq_set_status_flags(ipi_base + i, IRQ_HIDDEN); > } > > + if (n > nr_ipi) > + set_smp_dynamic_ipi(ipi_base + nr_ipi); From thinking about this patch more, I'm guessing that the biggest objection someone could have is that this uses up the "last" IPI slot in any systems that are stuck with only 8. Is that the reason that this patch series stagnated in the past, or was it something else? If this is truly the concern that people have, it doesn't look like it would be terribly hard to combine the existing IPI_CPU_STOP and IPI_CPU_CRASH_STOP. Presumably we could just get rid of the "crash stop" IPI and have the normal "stop" IPI do the crash if "waiting_for_crash_ipi" is non-zero. If that's the thing blocking the series from moving forward then I can add that to the series, or we could just wait until someone actually needs another IPI. ;-) -Doug